Systems and methods for data transfers between memory cells
First Claim
1. A memory system comprising:
- a pair of first-level sense amplifiers, each configured to be selectively coupled to a data line which is coupled to a memory cell array;
a second-level sense amplifier configured to be selectively coupled to the data line; and
a processor coupled to the first-level sense amplifiers and the second-level sense amplifier and configured tocontrol a source one of the first-level sense amplifiers to place data from a corresponding memory cell on the data line,control the second-level sense amplifier to maintain the data on the data line, andcontrol a destination one of the first-level sense amplifiers to read the data on the data line into a corresponding memory cell.
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Accused Products
Abstract
Systems and methods for reducing the latency of data transfers between memory cells by enabling data to be transferred directly between sense amplifiers in the memory system. In one embodiment, a memory system uses a conventional DRAM memory structure having a pair of first-level sense amplifiers, a second-level sense amplifier and control logic for the sense amplifiers. Each of the sense amplifiers is configured to be selectively coupled to a data line. In a direct data transfer mode, the control logic generates control signals that cause the sense amplifiers to transfer data from a first one of the first-level sense amplifiers (a source sense amplifier) to the second-level sense amplifier, and from there to a second one of the first-level sense amplifiers (a destination sense amplifier.) The structure of these sense amplifiers is conventional, and the operation of the system is enabled by modified control logic.
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Citations
20 Claims
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1. A memory system comprising:
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a pair of first-level sense amplifiers, each configured to be selectively coupled to a data line which is coupled to a memory cell array; a second-level sense amplifier configured to be selectively coupled to the data line; and a processor coupled to the first-level sense amplifiers and the second-level sense amplifier and configured to control a source one of the first-level sense amplifiers to place data from a corresponding memory cell on the data line, control the second-level sense amplifier to maintain the data on the data line, and control a destination one of the first-level sense amplifiers to read the data on the data line into a corresponding memory cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method implemented in a memory system having a pair of first-level sense amplifiers and a second-level sense amplifier, each sense amplifier being configured to be selectively coupled to a data line which is coupled to a memory cell array, the method comprising:
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controlling a source one of the first-level sense amplifiers to place data from a corresponding memory cell on the data line, controlling the second-level sense amplifier to maintain the data on the data line, and controlling a destination one of the first-level sense amplifiers to read the data on the data line into a corresponding memory cell. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification