Method and circuit for driving word line of memory cell

• US 7,808,858 B2
• Filed: 10/19/2007
• Issued: 10/05/2010
• Est. Priority Date: 12/27/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Jung-bae, Lee, Yun-sang
• Primary Examiner(s): Dinh; Son
• Application Number:
  US11/875,171
• Publication Number:
  US 20080159055A1
• Time in Patent Office: 1,082 Days
• Field of Search: 365/230.06, 365/203, 365/189.08
• US Class Current: 365/230.06
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A method and circuit are provided for driving a word line. The word line driving circuit includes first and second power drivers, a switching unit and a word line driver. The first power driver is driven to a boosting voltage level and the second power driver is driven to an internal power voltage level. The switching unit transfers a first output of the first power driver to the word line driver in response to a first switching signal and transfers a second output of the second power driver to the word line driver in response to a second switching signal. The word line driver alternately drives a word line to the first output and the second output transferred from the switching unit in response to a word line driving signal.

Claims

1. A method of driving a word line connected to memory cells, comprising:

enabling the word line to a boosting voltage level during a first period of a word line enable period; and

enabling the word line to an internal power voltage level during a second period of the word line enable period.

2. The method of claim 1, wherein the word line is enabled and data is re-stored in the memory cells during the first period of the word line enable period.

3. The method of claim 1, further comprising:

enabling the word line to the boosting voltage level during a third period of the word line enable period.

4. The method of claim 1, further comprising:

applying a ground voltage level to the word line during a word line disable period.

5. The method of claim 1, wherein the boosting voltage comprises the sum of the internal power voltage and a threshold voltage of the memory cells.

6. The method of claim 1, wherein the internal power voltage is used to drive array blocks in which the memory cells are arranged.

7. The method of claim 3, wherein the second period of the word line enable period is between the first period of the word line enable period and the third period of the word line enable period.

8. A word line driving circuit comprising:

a first power driver driven to a boosting voltage level;

a second power driver driven to an internal power voltage level;

a switching unit for transferring a first output of the first power driver to a word line driver in response to a first switching signal and for transferring a second output of the second power driver to the word line driver in response to a second switching signal;

the word line driver for alternately driving a word line to the first output and the second output transferred from the switching unit in response to a word line driving signal; and

a first switching signal generator and a second switching signal generator for respectively generating the first switching signal and the second switching signal in response to an active signal, a word line enable signal, a sense AMP enable signal, a pre-charge signal, a word line disable signal, and a write enable signal.

9. The word line driving circuit of claim 8, wherein the first power driver comprises an inverter connected between a boosting voltage source and a ground voltage.

10. The word line driving circuit of claim 8, wherein the second power driver comprises an inverter connected between an internal power voltage source and a ground voltage.

11. The word line driving circuit of claim 8, wherein the switching unit comprises:

a first PMOS transistor connected between the first power driver and the word line driver and having a gate connected to the first switching signal; and

a second PMOS transistor connected between the second power driver and the word line driver and having a gate connected to the second switching signal.

12. The word line driving circuit of claim 8, wherein the first switching signal generator comprises:

a first NAND gate for inputting the active signal and the word line enable signal;

a first NOR gate for inputting an output of the first NAND gate and the sense AMP enable signal;

a second NAND gate for inputting the pre-charge signal, the word line disable signal, and the write enable signal;

an inverter for inputting an output of the second NAND gate; and

a second NOR gate for inputting outputs of the first NOR gate and the inverter and outputting the first switching signal.

13. The word line driving circuit of claim 8, wherein the second switching signal generator comprises:

a first NAND gate for inputting the active signal, the word line enable signal, and the sense AMP enable signal;

an inverter for inputting an output of the first NAND gate;

a second NAND gate for inputting the pre-charge signal, the word line disable signal, and the write enable signal; and

a third NAND gate for inputting outputs of the inverter and the second NAND gate and outputting the second switching signal.

14. The word line driving circuit of claim 8, wherein the word line driver comprises:

a PMOS transistor comprising a gate connected to the word line driving signal, a source connected to an output of the switching unit, and a drain connected to the word line; and

an NMOS transistor comprising a gate connected to the word line driving signal, a source connected to a ground voltage, and a drain connected to the word line.