XFP transceiver with 8.5G CDR bypass

• US 7,809,275 B2
• Filed: 03/07/2005
• Issued: 10/05/2010
• Est. Priority Date: 06/25/2002
• Status: Active Grant

• Current Assignee: II-VI Delaware, Inc. (Coherent Corp.)
• Original Assignee: Finisar Corporation (II-VI Incorporated)
• Inventors: Zhou, Yuxin, Vu, Huy Anh, Chen, Jiashu, Aronson, Lewis B., Mason, Thomas Gordon Beck, Giaretta, Giorgio
• Primary Examiner(s): Phan; Hanh
• Application Number:
  US11/073,452
• Publication Number:
  US 20050169585A1
• Time in Patent Office: 2,038 Days
• Field of Search: 398/135, 398/136, 398/137, 398/139, 398/138, 398/158, 398/159, 398/162, 398/163, 398/164, 398/128, 398/2, 398/3, 398/9, 398/10, 398/15, 398/16, 398/17, 398/25, 398/26, 398/27, 398/31, 398/33, 398/38, 398/130, 398/154, 398/155, 398/22, 398/23, 398/24, 398/5, 398/177, 398/175, 385/88, 385/89, 385/90, 385/92, 385/93, 375/219, 375/211, 375/212, 375/214, 370/217, 370/241, 370/404, 370/406
• US Class Current: 398/135
• CPC Class Codes: G02B 6/2821 using lateral coupling between contiguous fibres to split or combine optical signals
• CPC Class Codes: H04B 10/40 Transceivers
• CPC Class Codes: H04L 25/242 with retiming
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

This disclosure concerns transceivers that include CDR bypass functionality. In one example, a 10 G XFP transceiver module includes integrated CDR functionality for reducing jitter. The 10 G XFP transceiver module also implements CDR bypass functionality so that the CDR can be bypassed at rate less than about 10 Gb/s, such as the Fibre Channel 8.5 Gb/s rate for example.

Claims

1. A transceiver module, comprising:

a TOSA;

a ROSA;

receiver eye opener circuitry including a first input configured to receive a first serial electrical data stream from the ROSA, and further including a first output through which the first serial electrical data stream passes, the first serial electrical data stream having a jitter value that is lower at the first output than at the first input, wherein the first serial electrical data stream is transmitted to a host;

transmitter eye opener circuitry including a second input configured to receive a second serial electrical data stream from the host, and further including a second output through which the second serial electrical data stream passes to the TOSA, the second serial electrical data stream having a jitter value that is lower at the second output than at the second input; and

bypass circuitry configured so that at least one of the serial electrical data streams bypasses corresponding eye opener circuitry when the at least one serial electrical data stream has a data rate less than about 10 Gb/s, and wherein the at least one of the serial electrical data streams that bypasses the corresponding eye opener circuitry is transmitted to or received from the host.

2. The transceiver as recited in claim 1, wherein the bypass circuitry is configured to permit at least one of the serial electrical data streams to bypass corresponding eye opener circuitry when the at least one serial electrical data stream has a data rate of about 8.5 Gb/s.

3. The transceiver as recited in claim 1, wherein the transceiver is compatible with the Fibre Channel protocol.

4. The transceiver as recited in claim 1, wherein the transceiver is substantially compliant with the XFP MSA.

5. The transceiver as recited in claim 1, wherein the bypass circuitry is configured so that for a data rate less than about 10 Gb/s:

the first serial electrical data stream bypasses the receiver eye opener circuitry; and

the second serial electrical data stream bypasses the transmitter eye opener circuitry.

6. The transceiver as recited in claim 1, wherein the bypass circuitry comprises first and second portions, the first portion corresponding to the transmitter eye opener circuitry and the second portion corresponding to the receiver eye opener circuitry.

7. The transceiver as recited in claim 1, wherein the receiver eye opener circuitry and transmitter eye opener circuitry each comprise a respective CDR, multiplexer, and retimer arranged in series.

8. The transceiver as recited in claim 1, wherein operation of the receiver eye opener circuitry and transmitter eye opener circuitry is responsive to a detected data rate.

9. The transceiver as recited in claim 1, wherein bypass of the at least one serial electrical data stream occurs automatically.

10. The transceiver as recited in claim 1, further comprising diagnostics circuitry configured to provide information concerning the performance of at least one of the ROSA;

and, the TOSA.

11. A transceiver module, comprising:

a plurality of components that are substantially compliant with the XFP MSA and are compatible for use in a Fibre Channel system, the plurality of components including;

a TOSA;

a ROSA;

receiver eye opener circuitry including a first input configured to receive a first serial electrical data stream from the ROSA, and further including a first output through which the first serial electrical data stream passes, the first serial electrical data stream having a jitter value that is lower at the first output than at the first input, wherein the first serial electrical data stream at the first output is delivered to a host;

transmitter eye opener circuitry including a second input configured to receive a second serial electrical data stream from the host, and further including a second output through which the second serial electrical data stream passes to the TOSA, the second serial electrical data stream having a jitter value that is lower at the second output than at the second input; and

bypass circuitry configured so that at least one of the serial electrical data streams bypasses corresponding eye opener circuitry when the at least one serial electrical data stream has a data rate of about 8.5 Gb/s, wherein the at least one of the serial electrical data streams that bypasses the corresponding eye opener circuitry is delivered to or received from the host.

12. The transceiver module as recited in claim 11, wherein the bypass circuitry is configured to operate in connection with one of:

an LOL signal;

an LOS signal; and

, a bypass signal.

13. The transceiver module as recited in claim 11, wherein the bypass circuitry is configured to permit at least one of the serial electrical data streams to bypass corresponding eye opener circuitry when the at least one serial electrical data stream has a data rate that falls within a predetermined range of bypass data rates.

14. The transceiver module as recited in claim 11, further comprising bypass control circuitry in communication with the bypass circuitry and configured to receive and transmit signals concerning operation of the bypass circuitry.

15. The transceiver module as recited in claim 14, wherein the bypass control circuitry is configured for at least one of:

manual control; and

, automatic operation.

16. A transceiver module, comprising:

a TOSA;

a ROSA;

receiver eye opener circuitry including a first input configured to receive a first serial electrical data stream from the ROSA, and further including a first output through which the first serial electrical data stream passes, the first serial electrical data stream having a jitter value that is lower at the first output than at the first input, wherein the first serial electrical data stream is transmitted to a host;

transmitter eye opener circuitry including a second input configured to receive a second serial electrical data stream from the host, and further including a second output through which the second serial electrical data stream passes to the TOSA, the second serial electrical data stream having a jitter value that is lower at the second output than at the second input; and

bypass circuitry configured to enable at least one of the serial electrical data streams to automatically bypass corresponding eye opener circuitry if the corresponding eye opener circuitry is not locked onto that serial electrical data stream, wherein the corresponding eye opener circuitry is configured to lock onto data streams having a data rate of less than about 8.5 Gb/s.

17. The transceiver module as recited in claim 16, wherein an ability of the eye opener circuitry to lock onto a serial electrical data stream is a function of a data rate associated with that data stream.

18. The transceiver module as recited in claim 16, wherein automatic bypass of corresponding eye opener circuitry occurs based upon generation of a loss of lock (LOL) signal by the corresponding eye opener circuitry.

19. The transceiver module as recited in claim 16, wherein the transceiver module is protocol agnostic.