Method and system for a power switch with a slow in-rush current

• US 7,809,408 B2
• Filed: 12/28/2006
• Issued: 10/05/2010
• Est. Priority Date: 12/06/2006
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Lee, Chungyeol Paul
• Primary Examiner(s): Nguyen; Duc M
• Application Number:
  US11/617,343
• Publication Number:
  US 20080137257A1
• Time in Patent Office: 1,377 Days
• Field of Search: 455/572, 455/343, 455/127.1, 323/908, 323/277, 323/289, 361/93.9
• US Class Current: 455/572
• CPC Class Codes: H03K 17/163 Soft switching
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: Y10S 323/908 Inrush current limiters

Abstract

Aspects of a method and system for a power switch with a slow in-rush current are presented. Aspects of the system may include at least one resistive component, which is coupled between an input control signal and an output stage circuit of a power switch circuit, so as to limit a peak transient current level, which may result from in-rush current delivered by the power switch circuit to a load impedance circuit during a transient time interval during which a voltage level across the load impedance circuit may rise or fall from an initial voltage level to a quiescent voltage level.

Claims

1. A method for electronic power supply control, the method comprising:

selecting a resistance of at least one resistive component, which is coupled between an input control signal and an output stage circuit of a power switch circuit, wherein said power switch circuit comprises a plurality of buffers coupled between said input control signal and said output stage circuit, so as to limit a peak transient current level, said peak transient current level results from in-rush current delivered by said power switch circuit to a load impedance circuit during a transient time interval during which a voltage level across said load impedance circuit rises or falls from an initial voltage level to a quiescent voltage level; and

limiting a rate of change of said voltage level across said load impedance circuit during said rise or fall from said initial voltage level to said quiescent voltage level, wherein said limiting of said rate of change of said voltage level across said load impedance limits said peak transient current level, wherein said change in voltage is caused by a change in voltage generated by at least one of said plurality of buffers.

2. The method according to claim 1, wherein said power switch circuit is coupled between a power supply source circuit and said load impedance circuit.

3. The method according to claim 2, wherein said quiescent voltage level is derived from a source voltage level generated by said power supply source circuit.

4. The method according to claim 3, comprising supplying said quiescent voltage level to said load impedance circuit by applying said input control signal to said power switch circuit.

5. The method according to claim 1, wherein said at least one resistive component is one or both of:

at least one resistor, and at least one transistor.

6. The method according to claim 5, wherein said resistive value for said at least one transistor is determined by selecting a size for at least one physical dimension of said at least one transistor.

7. The method according to claim 5, wherein said resistive value for said at least one resistor is variable.

8. The method according to claim 1, wherein said load impedance circuit is one or more of:

at least one component circuit within a receiver circuit, at least one component circuit within a transmitter circuit, at least one low noise amplifier circuit, at least one power amplifier circuit, and at least one processor circuit.

9. The method according to claim 1, comprising limiting said rate of change of said voltage level based on said selected resistance of at least one resistive component.

10. A system for electronic power supply control, the system comprising:

at least one resistive component, which is coupled between an input control signal and an output stage circuit of a power switch circuit, wherein said power switch circuit comprises a plurality of buffers coupled between said input control signal and said output stage circuit, so as to limit a peak transient current level, said peak transient current level results from in-rush current delivered by said power switch circuit to a load impedance circuit during a transient time interval during which a voltage level across said load impedance circuit rises or falls from an initial voltage level to a quiescent voltage level; and

said power switch circuit is operable to limit a rate of change of said voltage level across said load impedance circuit during said rise or fall from said initial voltage level to said quiescent voltage level, wherein said limiting of said rate of change of said voltage level across said load impedance limits said peak transient current level, wherein said change in voltage is caused by a change in voltage generated by at least one of said plurality of buffers.

11. The system according to claim 10, wherein said power switch circuit is coupled between a power supply source circuit and said load impedance circuit.

12. The system according to claim 11, wherein said quiescent voltage level is derived from a source voltage level generated by said power supply source circuit.

13. The system according to claim 12, wherein said power switch circuit is operable to supply said quiescent voltage level to said load impedance circuit by applying said input control signal to said power switch circuit.

14. The system according to claim 10, wherein said at least one resistive component is one or both of:

at least one resistor, and at least one transistor.

15. The system according to claim 14, wherein said resistive value for said at least one transistor is determined by selecting a size for at least one physical dimension of said at least one transistor.

16. The system according to claim 14, wherein said resistive value for said at least one resistor is variable.

17. The system according to claim 10, wherein said load impedance circuit is one or more of:

at least one component circuit within a receiver circuit, at least one component circuit within a transmitter circuit, at least one low noise amplifier circuit, at least one power amplifier circuit, and at least one processor circuit.

18. The system according to claim 10, wherein said power switch circuit is operable to limit said rate of change of said voltage level based on said selected resistance of said at least one resistive component.