Apparatus and method for measuring phase noise/jitter in devices under test

• US 7,809,517 B1
• Filed: 09/07/2007
• Issued: 10/05/2010
• Est. Priority Date: 09/07/2007
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Zuckerman, Lawrence H.
• Primary Examiner(s): Cosimano; Edward R
• Application Number:
  US11/899,849
• Time in Patent Office: 1,124 Days
• Field of Search: 734/321, 738/658, 738/659, 738/665, 324/73.1, 324/76.11, 324/76.77, 324/158.1, 324/500, 324/509, 324/511, 324/512, 324/521, 324/527, 324/537, 324/754, 324/765, 327/1, 327/2, 327/3, 340/500, 340/540, 340/635, 340/653, 340/657, 340/658, 702/1, 702/57, 702/58, 702/66, 702/70, 702/72, 702/79, 702/108, 702/109, 702/117, 702/124, 702/126, 702/127, 702/187, 702/189
• US Class Current: 702/72
• CPC Class Codes: G01R 31/31709 Jitter measurements; Jitter generators measuring jitter, noise figure or signal-to-noise ratio per se G01R29/26; analysis of tester signals G01R31/31901
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation

Abstract

A system for testing integrated circuit products and other devices under test (DUT) includes a DUT tester, which stimulates the devices under test and analyzes signals from the devices under test. A device interface board transports signals between the DUT tester and the devices under test. A test board is coupled to the device interface board and used to generate measurements associated with the devices under test, such as phase noise or phase jitter measurements. The test board could, for example, include a phase detector for detecting a phase difference between two signals and a control loop for adjusting at least one of the two signals to maintain an average of zero DC volts at an output of the phase detector. A customization module could also be used to customize the test board. The customization module could include a phase shifter, a phase-locked loop synthesizer, and/or an oscillator.

Claims

1. A system comprising:

a device interface board configured to transport signals between a product tester and a device under test; and

a test board coupled to the device interface board, the test board configured to receive a signal from the device under test through the device interface board, the test board also configured to generate one or more measurements associated with at least one characteristic of the device under test, the test board comprising;

a phase detector configured to detect a phase difference between two signals, at least one of the two signals based on the signal from the device under test; and

a control loop configured to adjust at least one of the two signals to maintain an average of approximately zero direct current volts at an output of the phase detector.

2. The system of claim 1, wherein the test board is configured to generate one or more measurements associated with phase noise or phase jitter in the device under test.

3. The system of claim 1, wherein:

the test board further comprises a phase-locked loop synthesizer configured to generate a reference signal;

the phase detector is configured to detect a phase difference between the reference signal and the signal from the device under test; and

the control loop is configured to adjust the phase-locked loop synthesizer to maintain the average of approximately zero direct current volts at the output of the phase detector.

4. The system of claim 1, wherein:

the test board further comprises;

a splitter configured to split the signal from the device under test to produce first and second split signals;

a delay line configured to delay the first split signal; and

a phase shifter configured to shift a phase of the second split signal;

the phase detector is configured to detect a phase difference between the delayed first split signal and the shifted second split signal; and

the control loop is configured to adjust the phase shifter to maintain the average of approximately zero direct current volts at the output of the phase detector.

5. The system of claim 1, wherein:

the test board further comprises;

a phase-locked loop synthesizer configured to generate a reference signal, the reference signal for controlling a first oscillator; and

a second oscillator configured to generate an input signal for the phase-locked loop synthesizer;

the phase detector is configured to detect a phase difference between the signal from the device under test and a signal from the first oscillator; and

the control loop is configured to adjust the second oscillator to maintain the average of approximately zero direct current volts at the output of the phase detector.

6. The system of claim 1, further comprising:

a customization module coupled to the test board, the customization module configured to generate one or more signals used to generate the one or more measurements.

7. A system comprising:

a device interface board configured to transport signals between a product tester and a device under test; and

a test board coupled to the device interface board, the test board configured to receive a signal from the device under test through the device interface board, the test board also configured to generate one or more measurements associated with at least one characteristic of the device under test, the test board comprising;

a phase detector configured to detect a phase difference between two signals, at least one of the two signals based on the signal from the device under test;

a plurality of amplifiers, a first of the amplifiers configured to receive and amplify an output of the phase detector, one or more remaining amplifiers configured to receive and amplify an output of a prior amplifier; and

a switch configured to selectively output one of multiple signals received from the plurality of amplifiers.

8. The system of claim 7, wherein the test board further comprises:

a conversion unit configured to convert root mean square values into direct current values, the root mean square values based on the signals provided by the switch.

9. A system comprising:

a device interface board configured to transport signals between a product tester and a device under test;

a test board coupled to the device interface board, the test board configured to receive a signal from the device under test through the device interface board, the test board also configured to generate one or more measurements associated with at least one characteristic of the device under test; and

a customization module coupled to the test board, the customization module configured to generate one or more signals used to generate the one or more measurements, the customization module comprising at least one of;

a phase shifter, a phase-locked loop synthesizer, and an oscillator.

10. An apparatus comprising:

an interface configured to communicate with a device under test through a device interface board; and

circuitry configured to receive a signal from the device under test through the device interface board and to generate one or more measurements associated with at least one characteristic of the device under test, the circuitry comprising;

a phase detector configured to detect a phase difference between two signals, at least one of the two signals based on the signal from the device under test; and

a control loop configured to adjust at least one of the two signals to maintain an average of approximately zero direct current volts at an output of the phase detector.

11. The apparatus of claim 10, wherein the circuitry is configured to generate one or more measurements associated with phase noise or phase jitter in the device under test.

12. The apparatus of claim 10, wherein the circuitry further comprises:

a conversion unit configured to convert root mean square values into direct current values.

13. The apparatus of claim 10, wherein;

the circuitry further comprises a phase-locked loop synthesizer configured to generate a reference signal;

the phase detector is configured to detect a phase difference between the reference signal and the signal from the device under test; and

the control loop is configured to adjust the phase-locked loop synthesizer to maintain the average of approximately zero direct current volts at the output of the phase detector.

14. The apparatus of claim 10, wherein:

the circuitry further comprises;

a splitter configured to split the signal from the device under test to produce first and second split signals;

a delay line configured to delay the first split signal; and

a phase shifter configured to shift a phase of the second split signal;

the phase detector is configured to detect a phase difference between the delayed first split signal and the shifted second split signal; and

the control loop is configured to adjust the phase shifter to maintain the average of approximately zero direct current volts at the output of the phase detector.

15. The apparatus of claim 10, wherein;

the circuitry further comprises;

a phase-locked loop synthesizer configured to generate a reference signal, the reference signal for controlling a first oscillator; and

a second oscillator configured to generate an input signal for the phase-locked loop synthesizer;

the phase detector is configured to detect a phase difference between the signal from the device under test and a signal from the first oscillator; and

the control loop is configured to adjust the second oscillator to maintain the average of approximately zero direct current volts at the output of the phase detector.

17. The apparatus of claim 10, further comprising:

a customization module configured to provide one or more signals to the test board, the customization module comprising at least one of;

a phase shifter, a phase-locked loop synthesizer, and an oscillator.

16. An apparatus comprising:

an interface configured to communicate with a device under test through a device interface board; and

circuitry configured to receive a signal from the device under test through the device interface board and to generate one or more measurements associated with at least one characteristic of the device under test, the circuitry comprising;

a phase detector configured to detect a phase difference between two signals, at least one of the two signals based on the signal from the device under test;

a plurality of amplifiers, a first of the amplifiers configured to receive and amplify an output of the phase detector, one or more remaining amplifiers configured to receive and amplify an output of a prior amplifier; and

a switch configured to selectively output one of multiple signals received from the plurality of amplifiers.

18. A method comprising:

coupling a test board to a device interface board of a product tester, the device interface board configured to transport signals between the product tester and a device under test;

receiving a signal from the device under test at the test board; and

generating one or more measurements associated with phase noise or phase jitter in the device under test using the signal from the device under test;

wherein the test board comprises;

a phase detector configured to detect a phase difference between two signals, at least one of the two signals based on the signal from the device under test; and

a control loop configured to adjust at least one of the two signals to maintain an average of approximately zero direct current volts at an output of the phase detector.

19. The method of claim 18, further comprising:

coupling a customization module to the test board; and

providing one or more signals to the test board from the customization module for use in generating the one or more measurements, the customization module comprising at least one of;

a phase shifter, a phase-locked loop synthesizer, and an oscillator.

20. The method of claim 18, wherein the test board further comprises a conversion unit that converts root mean square values into direct current values.