Booth multiplier with enhanced reduction tree circuitry
First Claim
1. A method for performing Booth multiplication in a digital signal processor, the method comprising:
- determining, by the digital signal processor, a multiplicand, A, comprising a first plurality of bits and a multiplier, B, comprising a second plurality of bits;
performing, by the digital signal processor, radix-m Booth recoding on B to generate a first predetermined number, n, of multiplication factors, the n multiplication factors approximating one half of the number of the second plurality of bits;
generating, by the digital signal processor, n partial products using the n multiplication factors as multipliers of A;
in the event of a negative multiplication factor, forming, by the digital signal processor, a two'"'"'s complement of A by inverting the first plurality of bits of A and associating a sticky “
1”
to complete the two'"'"'s complementation; and
reducing, by the digital signal processor, the partial products in multiple stages of reduction to a set of sum and carry components of a pre-determined length; and
generating, based on the set of sum and carry components, by the digital signal processor, a product of A and B.
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Accused Products
Abstract
Techniques for the design and use of a digital signal processor, including processing transmissions in a communications (e.g., CDMA) system. A modified Booth multiplication system and process determine a multiplicand, A, and a multiplier, B. Radix-m, (e.g., radix-4) Booth recoding on B generates “n” multiplication factors, where “n,” an integer, is approximating one half of the number of the multiplier bits. “n” partial products are generated using the “n” multiplication factors as multipliers of A. Then, a multiplication tree is formed using radix-m Booth encoding. The multiplication tree includes multiplier bits associated to generate a multiplication factors. In the event of a negative multiplication factor, a two'"'"'s complement of A is formed by inverting the bits of A and associating a sticky “1” to complete the two'"'"'s complementation. Furthermore, multiplication factors are reduced in multiple stages to a form sum and carry components of a pre-determined length. The additive inverse of A×B is formed by using novel techniques to calculate the product of A and −B.
17 Citations
24 Claims
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1. A method for performing Booth multiplication in a digital signal processor, the method comprising:
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determining, by the digital signal processor, a multiplicand, A, comprising a first plurality of bits and a multiplier, B, comprising a second plurality of bits; performing, by the digital signal processor, radix-m Booth recoding on B to generate a first predetermined number, n, of multiplication factors, the n multiplication factors approximating one half of the number of the second plurality of bits; generating, by the digital signal processor, n partial products using the n multiplication factors as multipliers of A; in the event of a negative multiplication factor, forming, by the digital signal processor, a two'"'"'s complement of A by inverting the first plurality of bits of A and associating a sticky “
1”
to complete the two'"'"'s complementation; andreducing, by the digital signal processor, the partial products in multiple stages of reduction to a set of sum and carry components of a pre-determined length; and generating, based on the set of sum and carry components, by the digital signal processor, a product of A and B. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A system for operation in association with a digital signal processor for performing Booth multiplication in the digital signal processor, comprising:
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processing circuitry configured to determine a multiplicand, A, comprising a first plurality of bits and a multiplier, B, comprising a second plurality of bits; a multiplier block configured to perform radix-m Booth recoding on B to generate a first predetermined number, n, of multiplication factors, the n multiplication factors approximating one half of the number of the second plurality of bits; a plurality of multiplier units associated with the multiplier block configured to generate n partial products using the n multiplication factors as multipliers of A; inverter circuitry configured to form a two'"'"'s complement of A, in the event of a negative multiplication factor, by inverting the first plurality of bits of A and associating a sticky “
1”
to complete the two'"'"'s complementation; andreduction circuitry associated with the multiplier units configured to reduce the partial products in multiple stages of reduction to a set of sum and carry components of a pre-determined length and generate, based on the set of sum and carry components, a product of A and B. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A digital signal processor for operation in support of a personal electronics device, the digital signal processor performing Booth multiplication in a digital signal processor, the digital signal processor comprising:
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means for determining, by the digital signal processor, a multiplicand, A, comprising a first plurality of bits and a multiplier, B, comprising a second plurality of bits; means for performing, by the digital signal processor, radix-m Booth recoding on B to generate a first predetermined number, n, of multiplication factors the n multiplication factors approximating one half of the number of the second plurality of bits; means for generating, by the digital signal processor, n partial products using the n multiplication factors as multipliers of A; means for, forming, by the digital signal processor, in the event of a negative multiplication factor, a two'"'"'s complement of A by inverting the first plurality of bits of A and associating a sticky “
1”
to complete the two'"'"'s complementation;means for reducing, by the digital signal processor, the partial products in multiple stages of reduction to a set of sum and carry components of a pre-determined length; and means for generating, based on the set of sum and carry components, a product of A and B. - View Dependent Claims (14, 15, 16, 17, 18)
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19. A computer usable medium having computer readable program code embodied therein for performing Booth multiplication in a digital signal processor, comprising:
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computer readable program code for determining, by the digital signal processor, a multiplicand, A, comprising a first plurality of bits and a multiplier, B, comprising a second plurality of bits; computer readable program code for performing, by the digital signal processor, radix-m Booth recoding on B to generate a first predetermined number, n, of multiplication factors, the n multiplication factors approximating one half of the number of the second plurality of bits; computer readable program code for generating, by the digital signal processor, n partial products using the n multiplication factors as multipliers of A; computer readable program code for forming, by the digital signal processor, in the event of a negative multiplication factor, a two'"'"'s complement of A by inverting the first plurality of bits of A and associating a sticky “
1”
to complete the two'"'"'s complementation;computer readable program code for reducing, by the digital signal processor, the partial products in multiple stages of reduction to a set of sum and carry components of a pre-determined length; and computer readable program code for generating, based on the set of sum and carry components, a product of A and B. - View Dependent Claims (20, 21, 22, 23, 24)
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Specification