Dual-mode switch for multi-media card/secure digital (MMC/SD) controller reading power-on boot code from integrated flash memory for user storage

• US 7,809,862 B2
• Filed: 04/17/2009
• Issued: 10/05/2010
• Est. Priority Date: 12/02/2003
• Status: Expired due to Fees

• Current Assignee: Super Talent Technology, Corporation
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Ma, Abraham C., Lee, Charles C., Yu, I-Kang Frank
• Primary Examiner(s): CHEN, ALAN S
• Application Number:
  US12/426,189
• Publication Number:
  US 20090240865A1
• Time in Patent Office: 536 Days
• Field of Search: None
• US Class Current: 710/14
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.

Claims

1. A dual-mode switch comprising:

an upstream interface to a host bus for connecting to a host;

a plurality of downstream interfaces connecting to a plurality of memory blocks;

a virtual bridge for connecting the upstream interface to the plurality of downstream interfaces;

a transaction manager, coupled to control the virtual bridge to act as a hub by passing data packets from the host to the plurality of memory blocks through the virtual bridge when operating in a hub mode, but for acting as a single endpoint to the host when operating in a single-endpoint mode;

wherein the transaction manager passes data between the host and the plurality of memory blocks but intercepts and modifies packets from the host to generate secondary packets over the bus segments to the plurality of memory blocks when operating in the single-endpoint mode;

wherein the plurality of memory blocks and the bus segments are hidden from the host by the transaction manager when operating in the single-endpoint mode, but visible as endpoints to the host when operating in hub mode;

wherein the dual-mode switch operates in modes having multiple endpoints or a single endpoint for multiple downstream memory blocks;

mode logic, coupled to the transaction manager, for determining when to set the transaction manager in the hub mode and when to set the transaction manager in the single-endpoint mode; and

a virtual storage processor, coupled to the transaction manager, wherein the virtual storage processor further stripes the host data into data segments across multiple endpoints for storage in multiple downstream memory blocks.

2. The dual-mode switch of claim 1 wherein the transaction manager determines a plurality of memory capacities of the plurality of memory blocks presently connected to the plurality of downstream interfaces by the bus segments;

also the transaction manager reports a sum of the plurality of memory capacities to the host as a memory capacity of a single virtual memory device when operating in the single-endpoint mode,

whereby memory capacities are aggregated.

3. The dual-mode switch of claim 1 wherein the transaction manager re-orders secondary packets to the plurality of memory blocks on the bus segments relative to a packet order of corresponding packets on the host bus to initiate overlapping accesses of two of the plurality of memory blocks.

4. The dual-mode switch of claim 1 further comprising:

a striping unit for distributing data segments of equal size across multiple endpoints of the plurality of memory blocks.

5. An aggregating dual-mode switch comprising:

upstream interface means for connecting to a host bus to a host;

a plurality of downstream interface means, connected to bus segments, for serially interfacing to a plurality of memory blocks;

virtual bridge means for connecting the upstream interface means to the plurality of downstream interface means;

transaction manager means for controlling the virtual bridge means to act as a hub by passing packets from the host to the plurality of memory blocks through the virtual bridge means when operating in a hub mode, but for acting as a single endpoint to the host when operating in a single-endpoint mode;

a virtual storage processor, coupled to the transaction manager means, wherein the virtual storage processor further stripes the host data into data segments across multiple endpoints for storage in the plurality of memory blocks;

wherein the transaction manager means passes data between the host and the plurality of memory blocks but intercepts and modifies packets from the host to generate secondary packets over the bus segments to the plurality of memory blocks when operating in the single-endpoint mode;

wherein the plurality of memory blocks and the bus segments are hidden from the host by the transaction manager means when operating in the single-endpoint mode, but visible as endpoints to the host when operating in hub mode; and

whereby the dual-mode switch operates in modes having multiple endpoints or a single endpoint for multiple downstream memory blocks.

6. The aggregating dual-mode switch of claim 5 wherein the transaction manager means includes means for re-ordering the secondary packets to the plurality of memory blocks on the bus segments relative to a packet order of corresponding packets on the host bus to initiate overlapping accesses of two of the plurality of memory blocks.

7. The aggregating dual-mode switch of claim 5 wherein the host bus is a Universal-Serial-Bus (USB), a Peripheral Component Interconnect (PCI) Express bus, an integrated device electronics (IDE) bus, a serial ATA bus, or a serial attached small-computer system interface (SAS) bus.

8. The aggregating dual-mode switch of claim 5 wherein the bus segments are a Multi-Media Card (MMC) bus, a Secure Digital (SD) bus, a Universal-Serial-Bus (USB), a PCI Express bus, an IDE bus, a serial ATA bus, a serial attached small-computer system interface (SAS) bus, or parallel data lines and a synchronous clock.

9. The aggregating dual-mode switch of claim 5 further comprising:

striping means for distributing data segments of equal size across multiple endpoints of the plurality of memory blocks.