Methods of enabling the validation of an integrated circuit adapted to receive one of a plurality of configuration bitstreams

• US 7,810,059 B1
• Filed: 10/11/2007
• Issued: 10/05/2010
• Est. Priority Date: 10/11/2007
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Trimberger, Stephen M.
• Primary Examiner(s): Chiang; Jack
• Assistant Examiner(s): Dimyan; Magid Y
• Application Number:
  US11/974,387
• Time in Patent Office: 1,090 Days
• Field of Search: 716/4, 716/6, 716/16
• US Class Current: 716/136
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

Methods of enabling the validation of an integrated circuit adapted to receive one of a plurality of configuration bitstreams for a circuit design is disclosed. The method comprises analyzing a plurality of implementations for the circuit design; determining minimum timing constraints based upon all of the implementations for the circuit design; generating a representative implementation, based upon the plurality of implementations, which meets the determined minimum timing constraints for all of the implementations of the circuit design; and outputting the representative implementation.

Claims

1. A method of enabling the validation of an integrated circuit in a system for each implementation of a plurality of implementations for a circuit design in the integrated circuit using a representative implementation for the circuit design, the method comprising:

analyzing the plurality of implementations for the circuit design;

determining minimum timing constraints based upon each implementation of the plurality of implementations for the circuit design;

generating the representative implementation, based upon the plurality of implementations, wherein the representative implementation meets the determined minimum timing constraints for the plurality of implementations; and

outputting the representative implementation.

2. The method of claim 1, further comprising determining best-case and worst-case timing performances for the plurality of implementations for the circuit design, wherein determining minimum timing constraints comprises determining minimum timing constraints to meet the worst-case timing performance.

3. The method of claim 2, further comprising generating a cost function associated with the timing performance of the circuit design.

4. The method of claim 3, further comprising optimizing the timing of the representative implementation to the best-case timing performance without going under the minimum timing constraints.

5. The method of claim 3, wherein determining the minimum timing constraints comprises determining minimum path delays.

6. The method of claim 5, wherein generating the cost function comprises generating the cost function based upon minimum path delays between a primary input and a register.

7. The method of claim 5, wherein generating the cost function comprises generating the cost function based upon minimum path delays between a register and a primary output.

8. A method of enabling the validation of an integrated circuit in a system for each implementation of a plurality of implementations for a circuit design in the integrated circuit using a representative implementation for the circuit design, the method comprising:

determining best-case and worst-case timing performances for the plurality of implementations for the circuit design;

determining minimum timing constraints to meet the worst-case timing performance;

generating the representative implementation, based upon the plurality of implementations, which meets the determined minimum timing constraints of the plurality of implementations;

optimizing timing of the representative implementation to the best-case timing performance without going under the minimum timing constraints; and

outputting the representative implementation.

9. The method of claim 8, wherein determining the best-case and worst-case performances for the plurality of implementations comprises determining best-case and worst-case performances for the plurality of implementations for all nets of the circuit design.

10. The method of claim 9, wherein optimizing the timing of the representative implementation comprises generating a cost function to minimize a sum of amounts by which the minimum timing constraints for the nets is exceeded.

11. The method of claim 9, wherein optimizing the timing of the representative implementation comprises generating a cost function to minimize an amount by which the minimum timing constraint for any net is exceeded.

12. The method of claim 8, wherein determining the minimum timing constraints comprises establishing minimum path delays between registers.

13. The method of claim 8, wherein determining the minimum timing constraints comprises establishing minimum path delays between a primary input and a register or minimum path delays between a register and a primary output.

14. The method of claim 8, wherein optimizing the timing of the representative implementation comprises performing place and route operations to improve performance of the representative implementation.

15. A method of enabling the validation of an integrated circuit adapted to receive one of a plurality of configuration bitstreams for a circuit design, the method comprising:

analyzing a plurality of implementations for the circuit design;

determining minimum timing constraints based upon each implementation of the plurality of implementations for the circuit design;

generating, by a computer, a representative implementation, based upon the plurality of implementations, which meets the determined minimum timing constraints for the plurality of implementations;

analyzing a speed of a selected integrated circuit configured with the representative implementation;

adjusting the speed of the selected integrated circuit to avoid exceeding a predetermined speed; and

validating the plurality of implementations using the selected integrated circuit configured with the representative implementation.

16. The method of claim 15, wherein determining the minimum timing constraints comprises one of a group of steps consisting of:

determining minimum path delays between logic circuits;

determining minimum path delays between registers;

determining a minimum path delay between a primary input and a register; and

determining a minimum path delay between a register and a primary output.

17. The method of claim 15, further comprising optimizing timing of the representative implementation to a best-case timing performance without going under the minimum timing constraints.

18. The method of claim 17, wherein optimizing the timing of the representative implementation comprises minimizing a sum of amounts by which minimum path delays for all paths in the circuit design is exceeded.

19. The method of claim 17, wherein optimizing the timing of the representative implementation comprises minimizing an amount by which a minimum path delay for any path is exceeded.

20. The method of claim 15, further comprising validating a system having an integrated circuit using the representative implementation.