Vertical channel transistor structure and manufacturing method thereof

• US 7,811,890 B2
• Filed: 10/11/2006
• Issued: 10/12/2010
• Est. Priority Date: 10/11/2006
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Shih, Yen-Hao, Wu, Chia-Wei, Hsu, Tzu-Hsuan
• Primary Examiner(s): Landau; Matthew C
• Assistant Examiner(s): Booker; Vicki B
• Application Number:
  US11/545,575
• Publication Number:
  US 20080087946A1
• Time in Patent Office: 1,462 Days
• Field of Search: 438/157, 438/283, 438/268, 438/270, 257/E21.442, 257/E21.679, 257/E29.309
• US Class Current: 438/270
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/42352 with the gate at least partly formed in a trench
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is formed in a fin-shaped structure protruding from the substrate. The cap layer is deposited on the fin-shaped structure. The cap layer and the fin-shaped structure have substantially the same width. The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the fin-shaped structure. The gate is deposited on the charge trapping layer and on two vertical surfaces of the fin-shaped structure. The source and the drain are respectively positioned on two sides of the fin-shaped structure and opposite the gate.

Claims

1. A method of manufacturing a vertical channel transistor structure, comprising:

(a) providing a substrate;

(b) forming a first layer of cap material on the substrate and a second layer of cap material over the first layer of cap material;

(c) etching the second layer of cap material to form a patterned cap layer;

(d) trimming the patterned cap layer to form a second patterned cap layer of the cap material, the second patterned cap layer having a width less than that of the patterned cap layer;

(e) etching the first layer of cap material and the substrate using the second patterned cap layer as a mask to form a semiconductor fin-shaped structure protruding from the substrate, the semiconductor fin-shaped structure comprising two vertical surfaces;

(f) forming a multilayer charge trapping layer, including a first dielectric layer in contact with upper portions of the two vertical surfaces of the semiconductor fin-shaped structure, a dielectric charge trapping layer on the first dielectric layer, and a second dielectric layer on the dielectric charge trapping layer, the second patterned cap layer being between the multilayer charge trapping layer and the semiconductor fin shaped structure;

(g) forming a control gate material layer on the multilayer charge trapping layer;

(h) etching the control gate material layer to form at least a gate positioned on the two vertical surfaces of the semiconductor fin-shaped structure; and

(i) implanting ions in the semiconductor fin-shaped structure on two sides of the gate to form at least a source/drain.

2. The method according to claim 1, wherein the second layer of cap material comprises silicon nitride and the first layer of cap material comprises silicon oxide.

3. The method according to claim 1 including, before step (f), depositing a silicon oxide material adjacent the fin-shaped structure using high density plasma (HDP) deposition to cover lower portions of the vertical surfaces of the fin-shaped structure and leave upper portions of the vertical surfaces uncovered.

4. The method according to claim 2, wherein step (c) further comprises:

forming a first patterned photo-resist layer on the second cap layer;

etching the second cap layer to form the patterned cap layer; and

removing the first patterned photo-resist layer.

5. The method according to claim 1, wherein after step (e), the method further comprises:

removing the second patterned cap layer.

6. The method according to claim 5, wherein the multilayer charge trapping layer is positioned on a top surface and the two vertical surfaces of the fin-shaped structure.

7. The method according to claim 1, wherein in step (d), the width of the second patterned cap layer approximately ranges between 10 nm˜

60 nm.

8. The method according to claim 1, wherein step (c) adopts reactive ion etching (RIE) method.

9. The method according to claim 1, wherein the second layer of cap material comprises silicon nitride and step (d) uses hot-phosphoric-acid (H₃PO₄) to trim the patterned cap layer.

10. The method according to claim 1, wherein the second layer of cap material comprises silicon nitride.