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Semiconductor memory device with memory cells on multiple layers

  • US 7,812,390 B2
  • Filed: 07/13/2007
  • Issued: 10/12/2010
  • Est. Priority Date: 07/25/2006
  • Status: Expired due to Fees
First Claim
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1. A semiconductor memory device comprising:

  • a first substrate having at least one string comprising a first select transistor, a second select transistor, and first memory cells connected in series between the first and second select transistors of the first substrate; and

    a second substrate having at least one string comprising a first select transistor, a second select transistor, and second memory cells connected in series between the first and second select transistors of the second substrate,wherein a number of the first memory cells of the at least one string of the first substrate is different from a number of the second memory cells of the at least one string of the second substrate, andwherein the number of the second memory cells is less than the number of the first memory cells, and wherein a channel length of each of the second memory cells is longer than a channel length of each of the first memory cells.

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