Semiconductor memory device with memory cells on multiple layers
First Claim
1. A semiconductor memory device comprising:
- a first substrate having at least one string comprising a first select transistor, a second select transistor, and first memory cells connected in series between the first and second select transistors of the first substrate; and
a second substrate having at least one string comprising a first select transistor, a second select transistor, and second memory cells connected in series between the first and second select transistors of the second substrate,wherein a number of the first memory cells of the at least one string of the first substrate is different from a number of the second memory cells of the at least one string of the second substrate, andwherein the number of the second memory cells is less than the number of the first memory cells, and wherein a channel length of each of the second memory cells is longer than a channel length of each of the first memory cells.
1 Assignment
0 Petitions
Accused Products
Abstract
A semiconductor memory device includes a first substrate having at least one string including a first select transistor, a second select transistor, and first memory cells connected in series between the first and second select transistors of the first substrate. The semiconductor memory device further includes a second substrate having at least one string including a first select transistor, a second select transistor, and second memory cells connected in series between the first and second select transistors of the second substrate. The number of the first memory cells of the at least one string of the first substrate is different from a number of the second memory cells of the at least one string of the second substrate. For example, the number of second memory cells may be less than the number of first memory cells.
-
Citations
16 Claims
-
1. A semiconductor memory device comprising:
-
a first substrate having at least one string comprising a first select transistor, a second select transistor, and first memory cells connected in series between the first and second select transistors of the first substrate; and a second substrate having at least one string comprising a first select transistor, a second select transistor, and second memory cells connected in series between the first and second select transistors of the second substrate, wherein a number of the first memory cells of the at least one string of the first substrate is different from a number of the second memory cells of the at least one string of the second substrate, and wherein the number of the second memory cells is less than the number of the first memory cells, and wherein a channel length of each of the second memory cells is longer than a channel length of each of the first memory cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A semiconductor memory device, comprising:
-
a first silicon substrate having at least one string comprising a first select transistor, a second select transistor, and memory cells connected in series between the first select transistor and the second select transistor; a memory material layer having at least one string comprising a first select transistor, a second select transistor, and memory cells connected in series between the first select transistor and the second select transistor; a first plug connected to drains of the first select transistors; a first switch transistor configured to connect the first plug to a bit line via a second plug; a third plug connected to sources of the second select transistors; a second switch transistor configured to connect the third plug to a common source line; and a peripheral circuit block, on the first silicon substrate, configured to control the first and second select transistors and the memory cells in each of the at least one first silicon substrate string and the at least one memory material layer string, wherein a number of the memory cells in the at least one string of the memory material layer is less than a number of the memory cells in the at least one string of the first silicon substrate, and wherein a channel length of each of the memory cells in the at least one string of the memory material layer is longer than a channel length of each of the memory cells in the at least one string of the first silicon substrate. - View Dependent Claims (12, 13, 14, 15, 16)
-
Specification