Apparatus and method for the arithmetic over-ride of look up table outputs in a programmable logic device

• US 7,812,633 B1
• Filed: 10/20/2006
• Issued: 10/12/2010
• Est. Priority Date: 04/03/2006
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Lewis, David, Lee, Andy L., Schleicher, James G. II, Pan, Philip
• Primary Examiner(s): Tan; Vibol
• Assistant Examiner(s): Tabler; Matthew C
• Application Number:
  US11/584,308
• Time in Patent Office: 1,453 Days
• Field of Search: 326 37- 50
• US Class Current: 326/38
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables

Abstract

A programmable logic device having a Logic Element with an N-stage Look Up Table (LUT), dedicated hardware for performing a non-LUT logic function, and an over-ride element configured to selectively force a muxing stage within the N-stage LUT to select either one or more LUT configuration bit inputs or the output of the non-LUT logic function as the output of the LUT. In various embodiments, the non-LUT functions can include addition, subtraction, multiplication, division, digital signal processing, memory storage, etc.

Claims

1. A programmable logic device, comprising

a plurality of logic blocks organized in an array, each of the logic blocks including logic elements, a plurality of the logic elements including:

an N-stage look up table (LUT) structure having configuration bit inputs and a LUT output;

dedicated hardware for performing a non-LUT logic function and for generating a non-LUT logic function output, wherein the non-LUT logic function is one of the following;

addition, subtraction, multiplication, division, and digital signal processing; and

an over-ride element coupled to the LUT and configured to selectively force a stage within the N stage look up table to select either one or more of the configuration bit inputs or the non-LUT logic function output so that the selected one or more of the configuration bit inputs or the non-LUT logic function output is provided at the LUT output, wherein the over-ride element comprises a register and a configuration random access memory (RAM) bit that allows a user to selectively enable or disable the over-ride function.

2. The programmable logic device of claim 1, wherein the N stage LUT comprises a plurality of muxes organized into the N stages.

3. The programmable logic device of claim 1, wherein the over-ride element is applied to a mux or muxes of a selected stage of the N stage LUT.

4. The programmable logic device of claim 1, wherein the selected stage is followed by one or more of the N stages and the over-ride element is not applied to the mux or muxes of the stages following the selected stage of the N stage LUT.

5. The programmable logic device of claim 2, wherein the over-ride element is applied to all the muxes associated with a selected stage of the N stage LUT.

6. The programmable logic device of claim 2, wherein the over-ride element is applied to a subset of the muxes associated with the selected stage of the N stage LUT, allowing normal LUT logic functions to be provided in subsequent stages of the LUT.

7. The programmable logic device of claim 5, wherein the over-ride element is not applied to the second stage, allowing one of the configuration bit inputs to be provided to the subsequent stages in the LUT.

8. The programmable logic device of claim 5, wherein the over-ride element provided to the selected stage is user controlled, thereby allowing the user to provide either:

(i) one of the configuration bit inputs to be provided to the subsequent stage or stages in the LUT;

(ii) the non-LUT logic function output is to be provided to subsequent stage or stages in the LUT;

or

(iii) both one of the configuration bit inputs and the non-LUT logic function output to be provided to subsequent stage or stages in the LUT.

9. The programmable logic device of claim 1, wherein, by user controlling the over-ride element and the selectively forced stage within the N stage look up table, the output signal provided at the LUT output is:

(i) one of the configuration bit inputs;

(ii) the non-LUT logic function output;

or

(iii) a logic function derived from one of the configuration bit inputs and the non-LUT logic function output.

10. The programmable logic device of claim 1, wherein the look up table has one of the following configurations:

(i) six stages (N=6) and sixty-four configuration bit inputs (2⁶=64);

(ii) five stages (N=5) and thirty-two configuration bit inputs (2⁵=32);

(iii) four stages (N=4) and sixteen configuration bit inputs (2⁴=16);

(iv) three stages (N=3) and eight configuration bit inputs (2³=8);

(v) two stages (N=2) and 4 configuration bit inputs (2²=4);

(vi) one stage (N=1) and two configuration bit inputs (2¹=2);

or

(vii) more than six stages with more than sixty-four configuration bits.

11. The programmable logic device of claim 1, wherein the LUT output is provided to a logic element output through an output mux.

12. The programmable logic device of claim 11, wherein the output mux is coupled to a local interconnect within the logic element.

13. The programmable logic device of claim 11, wherein the output mux is coupled to a global interconnect that interconnects the logic blocks in the array.

14. The programmable logic device of claim 1, further comprising a configuration RAM bit, coupled to the over-ride element, and configured to control the over-ride element.

15. The programmable logic device of claim 1, further comprising

a logic element output coupled to receive the selected one or more of the configuration bit inputs or the non-LUT logic function output provided at the LUT output;

and

a interconnect including a plurality of horizontal and vertical interconnect lines interconnecting the plurality of logic blocks of the array, one or more of the horizontal or vertical lines being selectively connected to the logic element output so that the selected one or more of the configuration bit inputs or the non-LUT logic function output provided at the LUT output can be routed to the plurality of logic blocks in the array.

23. The programmable logic device of claim 1 wherein the non-LUT logic function is addition.

24. The programmable logic device of claim 1 wherein the non-LUT logic function is subtraction.

25. The programmable logic device of claim 1 wherein the non-LUT logic function is multiplication.

26. The programmable logic device of claim 1 wherein the non-LUT logic function is division.

27. The programmable logic device of claim 1 wherein the non-LUT logic function is digital signal processing, the dedicated hardware is a finite impulse response (FIR) filter.

28. The programmable logic device of claim 1 wherein the non-LUT logic function is digital signal processing, the dedicated hardware is an infinite impulse response (IIR) filter.

16. A logic element, comprising:

an N-stage look up table (LUT) having configuration bit inputs and a LUT output;

dedicated hardware for performing a non-LUT logic function and for generating a non-LUT logic function output, the non-LUT logic function output coupled to a selected stage of the N stage LUT, wherein the non-LUT logic function is one of the following;

addition, subtraction, multiplication, division, and digital signal processing; and

an over-ride element coupled to the selected stage of the N stage LUT and configured to control the output of the LUT to be either one of the configuration bit inputs or the non-LUT logic function output, wherein the over-ride element comprises a register and a configuration random access memory (RAM) bit that allows a user to selectively enable or disable the over-ride function.

17. The logic element of claim 16, wherein the over-ride element is user controlled, whereby the user can control the over-ride element to selectively force the output of the LUT to be one of the following:

(i) one of the configuration bit inputs of the LUT;

(ii) the non-LUT logic function output;

or

(iii) a logic function derived from one of the configuration bit inputs and the non-LUT logic function output.

18. The logic element of claim 16, wherein the LUT has one of the following configurations:

(i) six stages (N=6) and sixty-four configuration bit inputs (2⁶=64);

(ii) five stages (N=5) and thirty-two configuration bit inputs (2⁵=32);

(iii) four stages (N=4) and sixteen configuration bit inputs (2⁴=16);

(iv) three stages (N=3) and eight configuration bit inputs (2³=8);

(v) two stages (N=2) and 4 configuration bit inputs (2²=4);

(vi) one stage (N=1) and two configuration bit inputs (2¹=2);

or

(vii) more than six stages with more than sixty-four configuration bits.

19. A method comprising:

providing an N-stage look up table (LUT) having configuration bit inputs and a LUT output;

providing dedicated hardware for performing a non-LUT logic function and for generating a non-LUT logic function output, the non-LUT logic function output coupled to a selected stage of the N stage LUT, wherein the non-LUT logic function is one of the following;

addition, subtraction, multiplication, division, and digital signal processing; and

providing an over-ride element, coupled to the selected stage of the N stage LUT and configured to control the output of the LUT to be either one of the configuration bit inputs or the non-LUT logic function output, wherein the over-ride element comprises a register and a configuration random access memory (RAM) bit that allows a user to selectively enable or disable the over-ride function.

20. The method of claim 19, wherein the provided over-ride element is user controlled, whereby the user can control the over-ride element to selectively force the output of the LUT to be one of the following:

(i) one of the configuration bit inputs of the LUT;

(ii) the non-LUT logic function output;

or

(iii) a logic function derived from one of the configuration bit inputs and the non-LUT logic function output.

21. The method of claim 19, wherein the provided LUT has one of the following configurations:

(i) six stages (N=6) and sixty-four configuration bit inputs (2⁶=64);

(ii) five stages (N=5) and thirty-two configuration bit inputs (2⁵=32);

(iii) four stages (N=4) and sixteen configuration bit inputs (2⁴=16);

(iv) three stages (N=3) and eight configuration bit inputs (2³=8);

(v) two stages (N=2) and 4 configuration bit inputs (2²=4);

(vi) one stage (N=1) and two configuration bit inputs (2¹=2);

or

(vii) more than six stages with more than sixty-four configuration bits.

22. A programmable logic device comprising a dedicated circuit and a look up table (LUT), the LUT having multiple stages and an output circuit, wherein the dedicated circuit is coupled directly to a stage of the LUT, wherein the LUT is configurable so that a signal generated by the dedicated circuit and output by the LUT is routed through the stage, and wherein the dedicated circuit is configured to perform one of the following functions:

addition, subtraction, multiplication, division, and digital signal processing, wherein the over-ride element comprises a register and a configuration random access memory (RAM) bit that allows a user to selectively enable or disable the over-ride function.