PC-based computing system employing a silicon chip implementing parallelized GPU-driven pipelines cores supporting multiple modes of parallelization dynamically controlled while running a graphics application

• US 7,812,845 B2
• Filed: 10/26/2007
• Issued: 10/12/2010
• Est. Priority Date: 01/28/2004
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Lucid Information Technology, Ltd.
• Inventors: Remez, Offir, Bakalash, Reuven, Fogel, Efi
• Primary Examiner(s): Nguyen, Hau H
• Application Number:
  US11/978,226
• Publication Number:
  US 20080129744A1
• Time in Patent Office: 1,082 Days
• Field of Search: 345502-506, 345/519, 345/419, 345/520
• US Class Current: 345/505
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G06F 3/1423 controlling a plurality of local displays, e.g. CRT and flat panel display
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/505 considering the load
• CPC Class Codes: G06F 9/5083 Techniques for rebalancing the load in a distributed system
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 2210/52 Parallel processing
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2360/06 Use of more than one graphics processor to process data before displaying to one or more screens
• CPC Class Codes: G09G 5/363 Graphics controllers

Abstract

A PC-based computing system employing a silicon chip implementing parallelized GPU-driven pipelines cores supporting multiple modes of parallelization dynamically controlled while running a graphics application. The PC-based computing system includes system memory for storing software graphics applications, software drivers and graphics libraries, and an operating system (OS), stored in the system memory, and a central processing unit (CPU), for executing the OS, graphics applications, drivers and graphics libraries. The system also includes a CPU/memory interface module and a CPU bus. The routing unit (i) routes the stream of geometrical data and graphic commands from the graphics application to one or more of the GPU-driven pipeline cores, and (ii) routes pixel data output from one or more of GPU-driven pipeline cores during the composition of frames of pixel data corresponding to final images for display on the display surface. The control unit accepts commands from the software multi-pipe drivers, and controls components within the silicon chip, including the routing unit. The profiling unit profiles the performance of the GPU-driven pipeline cores and feeds back performance data to the software multi-pipe drivers, for dynamically determining and controlling the mode of parallelization during the generation of each frame of pixel data, while running a graphics application.

Claims

1. A PC-based computing system comprising:

system memory for storing software graphics applications, software drivers and graphics libraries, and;

an operating system (OS), stored in said system memory;

one or more graphics applications, stored in said system memory, for generating a stream of geometrical data and graphics commands supporting (i) the representation of one or more 3D objects in a scene having 3D geometrical characteristics and (ii) the viewing of images of said one or more 3D objects in said scene during an interactive process carried out between said PC-based computing system and a user of said PC-based computing system;

one or more graphics libraries, stored in said system memory, for storing data used to implement said stream of geometrical data and graphics commands;

a central processing unit (CPU), for executing said OS, said graphics applications, said drivers and said graphics libraries;

a CPU bus;

a CPU/memory interface module for interfacing with said CPU by way of said CPU bus;

a display surface for displaying said images by graphically displaying frames of pixel data;

a plurality of GPU-driven pipeline cores arranged in a parallel architecture and operating according to one or more parallelization modes of operation, determined during the generation of each said frame of pixel data, so that said GPU-driven pipeline cores process geometrical data and graphics commands in a parallel manner;

wherein said one or more parallelization modes of operation include a time division mode, an image division mode, and an object division mode;

a silicon chip having a routing unit and a control unit; and

software multi-pipe drivers, stored in said system memory;

wherein said routing unit (i) routes the stream of geometrical data and graphics commands from said graphics application to one or more of said GPU-driven pipeline cores, and (ii) routes pixel data output from one or more of said GPU-driven pipeline cores during the composition of each frame of pixel data corresponding to a final image, for display on said display surface;

wherein said control unit accepts commands from said software multi-pipe drivers, over said CPU bus, and controls components within said silicon chip, including said routing unit;

wherein said software multi-pipe drivers perform the following functions;

(i) controlling the operation of said silicon chip,

(ii) interacting with said OS and said graphics libraries,

(ii) dynamically determining and controlling said parallelization mode during the generation of each said frame of pixel data during the running of said one or more graphics applications, and

(iii) forwarding said stream of geometrical data and graphics commands, or a portion thereof, over said CPU bus to one or more of said GPU-driven pipeline cores; and

wherein, for each image of said one or more 3D objects to be generated and displayed on said display surface, the following operations are performed;

(i) said silicon chip uses said routing unit to distribute said stream of geometrical data and graphics commands, or a portion thereof, to said GPU-driven pipeline cores,

(ii) one or more of said GPU-driven pipeline cores process said stream of geometrical data and graphics commands, or a portion thereof, during the generation of each said frame, while operating in said parallelization mode, so as to generate pixel data corresponding to at least a portion of said image, and

(iii) said silicon chip uses said routing unit to route said pixel data output from one or more of said GPU-driven pipeline cores and compose a frame of pixel data, representative of the image of said one or more 3D objects, for display on said display surface.

2. The PC-based computing system of claim 1, wherein said silicon chip further comprises a profiling unit for profiling the performance of said GPU-driven pipeline cores and feeding back performance data to said software multi-pipe drivers.

3. The PC-based computing system of claim 1, wherein said silicon chip further comprises a memory unit for storing intermediate processing results from one or more of said multiple GPU-driven pipeline cores, and data required for composition and transferring frames of pixel data for display.

4. The PC-based computing system of claim 1, wherein said CPU/memory interface module is an I/O chip or chipset.

5. The PC-based computing system of claim 1, wherein each said GPU-driven pipeline core has a frame buffer (FB) for storing a fragment of pixel data.

6. The PC-based computing system of claim 1, wherein said geometrical data comprises a set of scene polygons, textures and vertex objects.

7. The PC-based computing system of claim 1, wherein said graphics commands includes commands selected from the group consisting of display lists and display vertex arrays.

8. The PC-based computing system of claim 1, wherein said graphics libraries are selected from the group consisting of OpenGL and DirectX.

9. The PC-based computing system of claim 1, wherein said software multi-pipe drivers coordinate the operation of said GPU-driven pipeline cores so as to generate a continuous sequence of frames of pixel data for displaying a sequence of images of said one or more 3D objects on said display surface.

10. The PC-based computing system of claim 1, wherein each pixel associated with a frame of pixel data includes attributes selected from the group consisting of color, alpha, position, depth, and stencil.

11. The PC-based computing system of claim 1, wherein when said parallelization mode of operation is said time division mode, each said GPU-driven pipeline core renders a different frame of pixel data for display on said display surface at a different moment of time.

12. The PC-based computing system of claim 1, wherein when said parallelization mode of operation is said image division mode, each said GPU-driven pipeline core renders a subset of the pixels used to compose each frame of pixel data to be displayed on said display surface.

13. The PC-based computing system of claim 1, wherein when said parallelization mode of operation is said object division mode, said one or more 3D objects which are to be displayed as an image consisting of a frame of pixels, are decomposed into said stream of geometrical data and graphics commands, and then are distributed to said GPU-driven pipeline cores for rendering the frame of pixel data compositing the image to be displayed on said display surface.

14. The PC-based computing system of claim 13, wherein each said 3D object is decomposable into a plurality of polygons, and wherein said geometrical data comprises the vertices of said polygons.

15. The PC-based computing system of claim 1, wherein said software multi-pipe drivers further comprise one or more of the following software modules installed in said system memory:

(1) a GPU drivers module for allowing said GPU-driven pipeline cores to interact with said OS and said graphics libraries;

(2) a distributed graphics functions control module for performing functions associated with carrying on said parallelization modes according to a parallelization policy management;

(3) a state monitoring driver module for continuously analyzing substantially all incoming commands, including state commands, transferring certain state commands and some of the data all of said GPU-driven pipeline cores so as to preserve the valid state across said GPU-driven graphics pipeline cores;

(4) an application profiling and analysis driver module for performing real-time continuous monitoring of application parameters in said PC-based computing system, identifying problem areas likely to cause data bottlenecks;

(5) parallelism policy management driver module for determining, on a per-frame basis, the parallelization mode of said GPU-driven pipeline cores, using the results of said application profiling and analysis driver module, and for such determination to be carried out by said control unit.

16. The PC-based computing system of claim 15, wherein said application profiling and analysis driver modules uses inputs from (i) registers in said multiple GPU-driven pipeline cores (ii) registers in said control unit, and (iii) graphics API commands.

17. The PC-based computing system of claim 1, wherein when said parallelization mode of operation is said object division mode of parallel operation, said one or more 3D objects which are to be displayed as an image consisting of a frame of pixels, are decomposed into said stream of geometrical data and graphics commands, and then are distributed to said GPU-driven pipeline cores for rendering the frame of pixel data compositing the image to be displayed on said display surface.

18. The PC-based computing system of claim 1, wherein said dynamically determining and controlling said parallelization mode during any particular frame of pixel data generation and display is based on factors including the time required to render previous frames of pixel data and bottlenecks exhibited in vertex processing and pixel processing during the rendering of said previous frames of pixel data.

19. The PC-based computing system of claim 1, wherein said parallelization mode operation is based on any combination of said object division mode, said image division mode and said time division mode.

20. The PC-based computing system of claim 1, wherein during said dynamically determining and controlling said parallelization mode, said software multi-pipe drivers analyze collected parameters including data selected from the group consisting of:

memory speed, memory usage in bytes, total pixels rendered, geometric data entering rendering, frame rate, workload of each said GPU-driven pipeline core, load balance among said GPU-driven pipeline cores, volumes of transferred data, textures count, and depth complexity.

21. The PC-based computing system of claim 1, wherein the number of said GPU-driven pipeline cores has no architectural limit.

22. The PC-based computing system of claim 1, wherein said GPU-driven pipeline cores are organized in different parallelization modes for solving performance bottlenecks.

23. The PC-based computing system of claim 1, wherein at least one said GPU-driven pipeline core is realized on said silicon chip, along with said routing unit and said control unit.

24. The PC-based computing system of claim 1, which further comprises a graphics card, and wherein said silicon chip is mounted on said graphics card.

25. The PC-based computing system of claim 1, wherein said GPU-driven pipeline cores are realized on said silicon chip, along with said routing unit and said control unit, as a multi-processor system-on-a-chip (MP-SOC) architecture.