PC-based computing system employing a silicon chip of monolithic construction having a routing unit, a control unit and a profiling unit for parallelizing the operation of multiple GPU-driven pipeline cores according to the object division mode of parallel operation

• US 7,812,846 B2
• Filed: 10/26/2007
• Issued: 10/12/2010
• Est. Priority Date: 11/19/2003
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Lucid Information Technology, Ltd.
• Inventors: Bakalash, Reuven, Fogel, Efi, Remez, Offir
• Primary Examiner(s): Nguyen, Hau H
• Application Number:
  US11/978,239
• Publication Number:
  US 20080117219A1
• Time in Patent Office: 1,082 Days
• Field of Search: 345/505, 345/519, 345/506, 345/419, 345/520, 345502-504
• US Class Current: 345/519
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G06F 3/1423 controlling a plurality of local displays, e.g. CRT and flat panel display
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/505 considering the load
• CPC Class Codes: G06F 9/5083 Techniques for rebalancing the load in a distributed system
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 2210/52 Parallel processing
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2360/06 Use of more than one graphics processor to process data before displaying to one or more screens
• CPC Class Codes: G09G 5/363 Graphics controllers

Abstract

A PC-based computing system employing a silicon chip having a routing unit, a control unit and profiling unit for parallelizing multiple GPU-driven pipeline cores according to the object division mode of parallelization operation, during a graphics application. The PC-based computing system includes system memory for storing software graphics applications, software drivers and graphics libraries, and an operating system (OS), stored in the system memory, and a central processing unit (CPU), for executing the OS, graphics applications, drivers and graphics libraries. The system also includes a CPU/memory interface module and a CPU bus. The routing unit (i) routes the stream of geometrical data and graphic commands from the graphics application to one or more of the GPU-driven pipeline cores, and (ii) routes pixel data output from one or more of GPU-driven pipeline cores during the composition of frames of pixel data corresponding to final images for display on the display surface. The control unit accepts commands from the software multi-pipe drivers, and controls components within the silicon chip, including the routing unit. The profiling unit profiles the performance of the GPU-driven pipeline cores and feeds back performance data to the software multi-pipe drivers, for balancing the data load among the GPU-driven pipeline cores during the object division mode of parallelization operation.

Claims

1. A PC-based computing system comprising:

system memory for storing software graphics applications, software drivers and graphics libraries;

an operating system (OS), stored in said system memory;

one or more graphics applications, stored in said system memory, for generating a stream of geometrical data and graphics commands supporting (i) the representation of one or more 3D objects in a scene having 3D geometrical characteristics and (ii) the viewing of images of said one or more 3D objects in said scene during an interactive process carried out between said PC-based computing system and a user of said PC-based computing system;

one or more graphics libraries, stored in said system memory, for storing data used to implement said stream of geometrical data and graphics commands;

a central processing unit (CPU), for executing said OS, said one or more graphics applications, said drivers and said graphics libraries;

a CPU bus;

a CPU/memory interface module for interfacing with said CPU by way of said CPU bus;

a display surface for displaying said images by graphically displaying frames of pixel data;

a plurality of GPU-driven pipeline cores arranged in a parallel architecture and operating according to an object division mode of parallelization so that said GPU-driven pipeline cores process generated data and graphics commands in a parallel manner;

a silicon chip having a routing unit, a control unit, and a profiling unit; and

software multi-pipe drivers, stored in said system memory, and including a GPU driver module allowing said GPU-driven pipeline cores to interact with said OS and said graphics libraries;

wherein said routing unit (i) routes the stream of geometrical data and graphic commands from said one or more graphics applications to one or more of said GPU-driven pipeline cores, and (ii) routes pixel data output from one or more of said GPU-driven pipeline cores during the composition of each frame of pixel data corresponding to a final image, for display on said display surface;

wherein said control unit accepts commands from said software multi-pipe drivers, over said CPU bus, and controls components within said silicon chip, including said routing unit;

wherein said profiling unit profiles the performance of said GPU-driven pipeline cores and feeds back performance data to said software multi-pipe drivers, for balancing the data load among said GPU-driven pipeline cores during said object division mode of parallelization;

wherein said software multi-pipe drivers perform the following functions;

(i) controlling the operation of said silicon chip,

(ii) interacting with said OS and said graphics libraries, and

(iii) forwarding said stream of geometrical data and graphics commands, or a portion thereof, over said CPU bus to each said GPU-driven pipeline core; and

wherein, for each image of said one or more 3D objects to be generated and displayed on said display surface, the following operations are performed;

(i) said silicon chip uses said routing unit to distribute said stream of geometrical data and graphics commands, or a portion thereof, to said GPU-driven pipeline cores,

(ii) one or more of said GPU-driven pipeline cores process said stream of geometrical data and graphics commands, or a portion thereof, during the generation of each said frame, while operating in said object division mode of parallelization, so as to generate pixel data corresponding to at least a portion of said image, and

(iii) said silicon chip uses said routing unit to route said pixel data output from one or more of said GPU-driven pipeline cores and compose a frame of pixel data, representative of the image of said one or more 3D objects, for display on said display surface.

2. The PC-based computing system of claim 1, wherein said silicon chip further comprises a memory unit for storing intermediate processing results from one or more of said multiple GPU-driven pipeline cores, and data required for composition and transferring frames of pixel data for display.

3. The PC-based computing system of claim 1, wherein said CPU/memory interface module is an I/O chip or chipset.

4. The PC-based computing system of claim 1, wherein each said GPU-driven pipeline core has a frame buffer (FB) for storing a fragment of pixel data.

5. The PC-based computing system of claim 1, wherein said geometrical data comprises a set of scene polygons, textures and vertex objects.

6. The PC-based computing system of claim 1, wherein said graphics commands includes commands selected from the group consisting of display lists and display vertex arrays.

7. The PC-based computing system of claim 1, wherein said graphics libraries are selected from the group consisting of OpenGL and DirectX.

8. The PC-based computing system of claim 1, wherein said software multi-pipe drivers coordinate the operation of said GPU-driven pipeline cores so as to generate a continuous sequence of frames of pixel data for displaying a sequence of images of said one or more 3D objects on said display surface.

9. The PC-based computing system of claim 1, wherein each pixel associated with said frame of pixel data includes attributes selected from the group consisting of color, alpha, position, depth, and stencil.

10. The PC-based computing system of claim 1, wherein each said 3D object is decomposable into a plurality of polygons, and wherein said geometrical data comprises the vertices of said polygons.

11. The PC-based computing system of claim 1, wherein at least one said GPU-driven pipeline core is realized on said silicon chip, along with said routing unit and said control unit.

12. The PC-based computing system of claim 1, which further comprises a graphics card, and wherein said silicon chip is mounted on said graphics card.

13. The PC-based computing system of claim 1, wherein during said object division mode of parallelization, said one or more 3D objects which are to be displayed as an image consisting of a frame of pixels, are decomposed into said stream of geometrical data and graphics commands, and then distributed to said GPU-driven pipeline cores for rendering the frames of pixel data compositing the images to be displayed on said display surface.