High-speed signal testing system having oscilloscope functionality

• US 7,813,297 B2
• Filed: 07/12/2007
• Issued: 10/12/2010
• Est. Priority Date: 07/14/2006
• Status: Expired due to Fees

• Current Assignee: DFT Microsystems, Inc.
• Original Assignee: DFT Microsystems, Inc.
• Inventors: Hafed, Mohamed M.
• Primary Examiner(s): Ton; Dang T
• Assistant Examiner(s): Mansoury; Nourali
• Application Number:
  US11/776,865
• Publication Number:
  US 20080013456A1
• Time in Patent Office: 1,188 Days
• Field of Search: 370/252, 370/241, 370/249, 370/366, 375/226, 375/219, 375/224, 714/738, 714/742, 714/815
• US Class Current: 370/252
• CPC Class Codes: G01R 13/02 for displaying measured electric variables in digital form
• CPC Class Codes: G01R 31/3193 with comparison between actual response and known fault free response receiver details G01R31/31924
• CPC Class Codes: G01R 31/31932 Comparators

Abstract

A high-speed signal testing system that includes a digital circuitry for providing a pattern tester with oscilloscope functionality at minimal implementation cost. The digital circuitry includes a time-base generator that provides a high-speed repeating time-base signal. The time-base signal, in conjunction with a sub-sampler and an accumulation memory, allows the system to zoom in on, and analyze portions of, one or more bits of interest in a repeating pattern present on the signal under test. Such portions of interest include rising and falling edges and constant high and low bit values.

Claims

1. A system for testing a high-speed repeating data signal, comprising:

a time-base generator responsive to a reference clock signal so as to generate a high-speed repeating signal;

a one-bit voltage digitizer for digitizing the high-speed repeating data signal into a digitized signal as a function of the high-speed repeating signal;

a digital comparator for comparing the digitized signal to a selected digital value and outputting comparator results as a function of the high-speed repeating signal;

a bit-shift and frequency-divider block responsive to the high-speed repeating signal so as to produce a slowed clock signal;

a sub-sampler for sub-sampling the comparator results as a function of the slowed clock signal so as to output sub-sampled results;

a modulo N address counter, wherein N is greater than zero, for providing write addresses as a function of the high-speed repeating signal; and

an accumulation memory for storing ones of the sub-sampled results as a function of the slowed clock signal and corresponding respective ones of the write addresses.

2. The system of claim 1, wherein said one-bit voltage digitizer comprises a voltage comparator.

3. The system of claim 1, wherein said time-base generator includes modulation circuitry for generating a rapidly varying phase signal as a function of the reference clock signal.

4. The system of claim 3, wherein said time-base generator includes a phase-locked loop for receiving the rapidly varying phase signal and outputting the high-speed repeating signal.

5. The system of claim 3, wherein said modulation circuitry includes clock-selection circuitry for continually selecting from among differing-delay versions of the reference clock signal so as to generate the rapidly varying phase signal.

6. The system of claim 5, wherein said modulation circuitry further includes a delay element for receiving the reference clock signal and outputting a shifted clock signal phase-shifted relative to the reference clock signal, said clock-selection circuitry including a first multiplexer for receiving the reference clock signal and the shifted clock signal.

7. The system of claim 6, wherein said delay element is programmable in coarse increments.

8. The system of claim 6, wherein said first multiplexer includes an output and a select port, said modulation circuitry also including a selection signal generator in operative communication with said select port of said multiplexer and configured to generate a high-frequency selection signal for causing said multiplexer to continually select between the reference clock signal and the delayed clock signal.

9. The system of claim 8, wherein said selection signal generator comprises a circular memory clocked by the reference clock signal.

10. The system of claim 1, further comprising a selector for outputting the selected digital value, said selector for selecting between a bit pattern and a constant bit value.

11. The system of claim 1, further comprising a reference-pattern memory for storing a reference bit pattern having a length, said bit shift and frequency divider dividing the high-speed repeating signal the length.

12. The system of claim 1, further comprising a reference-pattern memory for storing a reference bit pattern having a length, said time-base generator having a time-base span, and the length and the time-base span having opposite evenness.

13. The system of claim 1, wherein said time-base generator has a time-base span and said accumulation memory has a length equal to the time-base span or a multiple of the time-base span.

14. The system of claim 1, further comprising a reference-pattern memory for storing a reference bit pattern having a length, said accumulation memory having a length of opposite evenness relative to the length of the reference bit pattern.

15. A system for testing a high-speed repeating data signal, comprising:

oscilloscope circuitry that includes;

a time-base generator responsive to a reference clock signal so as to generate a high-speed repeating signal;

a one-bit voltage digitizer for digitizing the high-speed repeating data signal into a digitized signal as a function of the high-speed repeating signal;

a reference pattern memory for storing a reference bit pattern having a length;

a selector for selecting between the reference bit pattern and a constant bit value so as to output a selected digital value;

a digital comparator for comparing the digitized signal to the selected digital value and outputting comparator results as a function of the high-speed repeating signal;

a bit-shift and frequency-divider block responsive to the high-speed repeating signal so as to produce a slowed clock signal, said bit shift and frequency divider block divides the high-speed repeating signal the length;

a sub-sampler for sub-sampling the comparator results as a function of the slowed clock signal so as to output sub-sampled results;

a modulo N address counter, wherein N is greater than zero, for providing write addresses as a function of the high-speed repeating signal; and

an accumulation memory for storing ones of the sub-sampled results as a function of the slowed clock signal and corresponding respective ones of the write addresses.

16. The system of claim 15, wherein said one-bit voltage digitizer comprises a voltage comparator.

17. The system of claim 15, wherein said time-base generator has a time-base span, and the length and the time-base span having opposite evenness.

18. The system of claim 15, wherein said time-base generator has a time-base span and said accumulation memory has a length equal to the time-base span or a multiple of the time-base span.

19. The system of claim 15, wherein said accumulation memory has a length of opposite evenness relative to the length of the reference bit pattern.

20. A method of implementing an oscilloscope to analyze a high-speed data signal, comprising:

digitizing the high-speed data signal into a one-bit digitized signal in response to a repeating a time-based span having a time-base span N;

comparing the one-bit digitized signal to a constant bit value in response to the repeating time-base signal so as to generate comparator results;

dividing the repeating time-base signal so as to create a slowed clock signal corresponding to high-speed data period;

sub-sampling the comparator results in response to the slowed clock signal so as to output sub-sampled results;

generating modulo N write addresses, wherein N is greater than zero, as a function of the repeating time-base signal; and

storing ones of said sub-sampled results in a memory in response to the slowed clock signal and corresponding respective ones of the write addresses.

21. The method of claim 20, wherein the storing of ones of the sub-sampled results includes accumulating the sub-sampled results so as to generate a thermometer code.

22. The method of claim 20, further comprising generating the repeating time-base signal as a function of continually selecting between clock signals of differing delay to create a composite signal and phase filtering the composite signal to achieve the repeating time-base signal.

23. The method of claim 22, wherein said continually selecting between the clock signals is performed using a selection signal, the method further including generating the selection signal as a function of the contents of a circular memory.

24. The method of claim 22, wherein said phase filtering of the composite signal comprises phase filtering the composite signal with a phase-locked loop.