Receiver with dual D.C. noise cancellation circuits

• US 7,813,702 B1
• Filed: 06/18/2007
• Issued: 10/12/2010
• Est. Priority Date: 03/27/2000
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: He, Runsheng
• Primary Examiner(s): Gesesse; Tilahun
• Application Number:
  US11/820,115
• Time in Patent Office: 1,212 Days
• Field of Search: 455/226.1, 455/67.13, 455/296, 455/209, 455/67.4, 455/63.1, 455/227.1, 455/226.4, 375/319
• US Class Current: 455/63.1
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22
• CPC Class Codes: H04L 25/063 Setting decision thresholds using feedback techniques only

Abstract

A receiver comprises an input circuit that receives an input signal. An error circuit generates an error signal based on the input signal. A first noise canceler generates a first noise cancellation signal based on the error signal. A second noise canceler generates a second noise cancellation signal based on the error signal. The input circuit is responsive to the second noise cancellation signal.

Claims

1. A receiver comprising:

an input circuit configured to receive an input signal;

an error circuit configured to generate an error signal based on the input signal;

a first noise canceler configured to generate a first noise cancellation signal based on the error signal;

a second noise canceler configured to generate a second noise cancellation signal based on the error signal;

a first feedback loop comprising the first noise canceler, the first feedback loop configured to receive the error signal;

a second feedback loop comprising the second noise canceler, the second feedback loop configured to receive (i) the first noise cancellation signal and (ii) the error signal;

a first summer configured to receive the second noise cancellation signal; and

a second summer configured to receive the first noise cancellation signal,

wherein the input circuit is responsive to the second noise cancellation signal.

2. The receiver of claim 1, further comprising an equalizer in communication with the input circuit.

3. The receiver of claim 2, wherein the equalizer comprises a feed forward/feedback equalizer.

4. The receiver of claim 2, further comprising an analog-to-digital converter responsive to the input circuit,

wherein the equalizer is responsive to the analog-to-digital circuit.

5. The receiver of claim 2, further comprising a first adder circuit that subtracts the first noise cancellation signal from an output of the equalizer.

6. The receiver of claim 5, further comprising a decision circuit configured to determine an estimate of the input signal based on an output of the first adder circuit.

7. The receiver of claim 6, wherein the error circuit comprises a second adder circuit configured to generate the error signal based on a difference between (i) an output of the decision circuit and (ii) the output of the first adder circuit.

8. The receiver of claim 1, wherein the first noise canceler comprises:

a scaler circuit configured to scale the error signal; and

an accumulator circuit configured to accumulate the scaled error signal.

9. The receiver of claim 1, wherein the second noise canceler comprises:

an adder circuit configured to generate an addition signal by adding the error signal and the first noise cancellation signal;

a scaler circuit configured to scale the addition signal; and

an accumulator circuit configured to accumulate the scaled addition signal.

10. The receiver of claim 1, wherein the second noise canceller generates the second noise cancellation signal based on the first noise cancellation signal and the error signal.

11. The receiver of claim 1, wherein each of the first noise canceler and the second noise canceler receives the error signal.

12. The receiver of claim 1, wherein the second noise canceler (i) receives the first noise cancellation signal and (ii) generates the second noise cancellation signal based on the first noise cancellation signal.

13. The receiver of claim 1, wherein:

the second noise canceler receives the error signal; and

the input circuit receives the second noise cancellation signal.

14. The receiver of claim 1, wherein:

the first summer receives the input signal and generates an adjustment signal; and

the second summer receives an equalized signal that is generated based on the adjustment signal.

15. A receiver comprising:

a first circuit that generates a first signal based on an input signal and a first noise cancellation signal;

an equalizer that generates an equalized signal based on the first signal;

a second circuit that generates a second signal based on a second noise cancellation signal and the equalized signal;

a decision circuit that generates an estimated original signal based on the second signal;

a third circuit that generates an error signal based on the estimated original signal and the second signal;

a first noise canceler that generates the first noise cancellation signal based on the error signal; and

a second noise canceler that generates the second noise cancellation signal based on the error signal.

16. The receiver of claim 15, wherein the second noise canceller generates the second noise cancellation signal based on the first noise cancellation signal and the error signal.

17. The receiver of claim 15, wherein the second noise cancellation signal has a shorter time latency than the first noise cancellation signal.

18. The receiver of claim 15, wherein the equalizer comprises a feed forward/feedback equalizer.

19. The receiver of claim 15, further comprising an analog-to-digital converter that receives the first signal,

wherein the equalizer is responsive to the analog-to-digital circuit.

20. The receiver of claim 15, wherein the first, second and third circuits comprise adder circuits.

21. The receiver of claim 15, wherein the first noise canceler comprises a scaler circuit that scales the error signal.

22. The receiver of claim 21, wherein the first noise canceler comprises an accumulator circuit that accumulates the scaled error signal.

23. The receiver of claim 15, wherein the second noise canceler comprises an adder circuit that adds the error signal and the first noise cancellation signal to generate an addition signal.

24. The receiver of claim 23, further comprising:

a scaler circuit that scales the addition signal; and

an accumulator circuit that accumulates the scaled addition signal.

25. A method comprising:

receiving an input signal;

generating an error signal based on the input signal;

generating a first noise cancellation signal based on the error signal via a first noise canceler;

generating a second noise cancellation signal based on the error signal via a second noise canceler; and

generating an adjusted signal based on the input signal and the second noise cancellation signal,

wherein generating the second noise cancellation signal comprises adding the error signal and the first noise cancellation signal to generate an addition signal.

26. The method of claim 25, further comprising equalizing the adjusted signal.

27. The method of claim 26, wherein the equalizing comprises feed forward/feedback equalizing.

28. The method of claim 26, further comprising converting the adjusted signal to a digital signal.

29. The method of claim 26, further comprising subtracting the first noise cancellation signal from an output of the equalizing.

30. The method of claim 29, further comprising determining an estimate of the input signal based on an output of the subtracting.

31. The method of claim 30, further comprising generating the error signal based on a difference between outputs of the determining and the subtracting.

32. The method of claim 25, wherein generating the first noise cancellation signal comprises:

scaling the error signal; and

accumulating the scaled error signal.

33. The method of claim 25, wherein generating the second noise cancellation signal comprises:

scaling the addition signal; and

accumulating the scaled addition signal.

34. The method of claim 25, further comprising generating the second noise cancellation signal based on the first noise cancellation signal and the error signal.

35. The method of claim 25, further comprising transmitting the error signal to a first noise canceler and to a second noise canceler.

36. A method comprising:

generating a first signal based on an input signal and a second noise cancellation signal;

generating an equalized signal based on the first signal;

generating a second signal based on a first noise cancellation signal and the equalized signal;

generating an estimated original signal based on the second signal;

generating an error signal based on the estimated original signal and the second signal;

generating the first noise cancellation signal based on the error signal; and

generating the second noise cancellation signal based on the error signal.

37. The method of claim 36, further comprising generating the second noise cancellation signal based on the first noise cancellation signal and the error signal.

38. The method of claim 36, wherein the second noise cancellation signal has a shorter time latency than the first noise cancellation signal.

39. The method of claim 36, wherein the equalizing comprises feed forward/feedback equalizing.

40. The method of claim 36, further comprising scaling the error signal.

41. The method of claim 40, further comprising accumulating the scaled error signal.

42. The method of claim 36, further comprising adding the error signal and the first noise cancellation signal to generate an addition signal.

43. The method of claim 42, further comprising:

scaling the addition signal; and

accumulating the scaled addition signal.

44. The method of claim 36, wherein generating the second signal comprises adding the equalized signal and the first noise cancellation signal.