Shared storage for multi-threaded ordered queues in an interconnect

• US 7,814,243 B2
• Filed: 06/01/2007
• Issued: 10/12/2010
• Est. Priority Date: 06/01/2007
• Status: Active Grant

• Current Assignee: META Platforms Technologies LLC (Meta Platforms, Inc. (f/k/a Facebook, Inc.))
• Original Assignee: Sonics Incorporated (Meta Platforms, Inc. (f/k/a Facebook, Inc.))
• Inventors: Hamilton, Stephen W.
• Primary Examiner(s): Kindred; Alford W
• Assistant Examiner(s): Abad; Farley J
• Application Number:
  US11/757,248
• Publication Number:
  US 20080301708A1
• Time in Patent Office: 1,229 Days
• Field of Search: 710/52, 710/54, 326/56, 709/234, 365/189.05, 711/118
• US Class Current: 710/52
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 9/466 Transaction processing

Abstract

In one embodiment, payload of multiple threads between intellectual property (IP) cores of an integrated circuit are transferred, by buffering the payload using a number of order queues. Each of the queues is guaranteed access to a minimum number of buffer entries that make up the queue. Each queue is assigned to a respective thread. A number of buffer entries that make up any queue is increased, above the minimum, by borrowing from a shared pool of unused buffer entries on a first-come, first-served basis. In another embodiment, an interconnect implements a content addressable memory (CAM) structure that is shared storage for a number of logical, multi-thread ordered queues that buffer requests and/or responses that are being routed between data processing elements coupled to the interconnect. Other embodiments are also described and claimed.

Claims

1. A system, comprising:

an integrated circuit having one or more data processing elements and one or more memory storage elements; and

an interconnect to which the data processing elements are coupled, the interconnect to route a plurality of requests and a plurality of responses between the data processing elements and the one or more memory storage elements,

wherein the interconnect implements a content addressable memory (CAM) structure that is shared storage for a plurality of logical, multi-thread ordered queues that make up entries in the CAM structure and buffer the requests from two or more threads from the data processing elements, the responses from two or more threads, or both, wherein each thread has its own unique identifier, and wherein a first multi-thread ordered queue is useable by a first request from a first thread with its own unique identifier (ID) during a first period of time and the same first multi-thread ordered queue is useable by a second request from a second thread with its own unique ID during a second period of time during the operation of the system; and

wherein each of the entries in the CAM structure has a key and a data word,

the key having first and second fields, the first field identifies a first multi-thread ordered queue through the unique ID, from among the plurality of multi-thread ordered queues, to which its entry is currently assigned, and the second field represents how many other entries precede this entry, in queue order, for the first multi-thread ordered queue, and

the data word contains a portion of a buffered request or response.

2. The system of claim 1, wherein each of the entries in the CAM structure has a key and a data word, the key identifies an associated multi-thread ordered queue and its associated thread, from among the plurality of multi-thread ordered queues, and the data word contains a portion of a buffered request or response in the associated thread, and when a first CAM entry is output following a match with an input key, the first CAM entry is invalidated and becomes available for re-use by the associated multi-thread ordered queue or a different multi-thread ordered queue.

3. The system of claim 1, wherein the CAM entries are managed so that at most one of the plurality of CAM entries matches any accessed key which is currently accessed and thus in use, and wherein the interconnect is a system bus and a memory interface to a first memory storage element is located downstream of the interconnect.

4. The system of claim 1, wherein the first field identifying the first multi-thread ordered queue through the unique ID is static for a duration of time its CAM entry is valid, and the CAM entry becomes invalidated in response to a) an accessed key matching the CAM entry and b) its data word being output.

5. The system of claim 1, wherein the second field representing how many other entries precede this CAM entry in queue order is dynamic and changes whenever an accessed key matches an entry that precedes this CAM entry, in queue order, for the first multi-thread ordered queue.

6. The system of claim 1 wherein a thread number is assigned to the first field when its CAM entry is written, and does not change as long as the CAM entry is in use.

7. A machine-readable storage medium having data and instructions stored therein which, when executed by a machine, cause the machine to generate a representation of the system of claim 1.

8. The machine-readable storage medium of claim 7, wherein the data and instructions are part of a stored electronic design automation (EDA) toolset for use in a System-on-a-Chip (SoC) design process that is to generate the representation of the system.

9. The system of claim 1, wherein the integrated circuit is a System-on-a-Chip (SoC) and the interconnect is pipelined to store and move the plurality of requests and responses in stages through the SoC.

10. An apparatus comprising:

an interconnect for an integrated circuit (IC), the interconnect to transfer a payload of multiple threads between a plurality of Intellectual Property (IP) cores of the integrated circuit that are coupled to the interconnect, wherein the interconnect implements a content addressable memory (CAM) structure that is shared storage for a plurality of multiple thread buffers that make up entries in the CAM structure and stores requests that are from two or more threads and that come from an initiator IP core and that are to be routed to a target IP core in the integrated circuit, and wherein a first multiple thread buffer is useable by a first request from a first thread with its own unique ID during a first period of time and the same first multiple thread buffer is useable by a second request from a second thread with its own unique ID during a second period of time during the operation of the apparatus;

wherein each of the entries in the CAM structure has a key and a data word,

the key having first and second fields, the first field identifies a first multiple thread buffer through the unique ID, from among a plurality of multiple thread buffers, to which its entry is currently assigned, and the second field represents how many other entries precede this entry, in queue order, for the first multiple thread buffer, and

the data word contains a portion of a buffered request or response.

11. The apparatus of claim 10, wherein the shared storage comprises an asynchronous multi-threaded ordered queue (MTOQ), the MTOQ being implemented as the combination of a single-threaded asynchronous ordered queue whose read port feeds a write port of a multi-threaded synchronous ordered queue in which the plurality of multiple thread buffers are implemented using the CAM structure.

12. The apparatus of claim 11, wherein the asynchronous multi-threaded ordered queue is a multi-thread First In First Out (FIFO) with non-blocking behavior and wherein the interconnect is a system bus and a memory interface to a first memory storage element is located downstream of the interconnect.

13. The apparatus of claim 10, wherein the CAM structure has a fixed number of buffer entries for each thread that is assigned to the CAM structure, and an amount shared buffer entries that may be used on a first-come, first-served basis by any of the threads assigned to the CAM after the allotted fixed number of buffer entries assigned for that thread has been exceeded.