Serialization of data for multi-chip bus implementation

• US 7,814,250 B2
• Filed: 04/27/2007
• Issued: 10/12/2010
• Est. Priority Date: 04/27/2007
• Status: Expired due to Fees

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Bracamontes Del Toro, Rocendo
• Primary Examiner(s): Dang; Khanh
• Application Number:
  US11/741,352
• Publication Number:
  US 20080270650A1
• Time in Patent Office: 1,264 Days
• Field of Search: 710/51, 710/60, 710/61, 710/71, 710/72, 710/110, 710/305, 710/306, 710/311, 710/316, 710/317, 341/100, 341/101
• US Class Current: 710/110
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

Bus communication for components of a system on a chip. In one aspect of the invention, a system includes a matrix operative to select destinations for information on buses connected to the matrix. A first serializer provided on a first device serializes information received from the matrix and sends the serialized information over a communication bus. A second serializer provided on a second device receives the serialized information and deserializes the serialized information, where the deserialized information is provided to a peripheral provided on the second device.

Claims

1. A system including bus communication, the system comprising:

a matrix operative to select destinations for information on buses connected to the matrix;

a first serializer coupled to the matrix and provided on a first device, the first serializer operative to serialize information received from the matrix and send the serialized information over a communication bus; and

a second serializer provided on a second device and coupled to the communication bus, the second serializer operative to receive the serialized information and deserialize the serialized information, wherein the deserialized information is provided to a peripheral provided on the second device, wherein each of the first and second serializers includes a mechanism operative to introduce automatic wait cycles in a communication protocol for the communication bus to allow serialization of the information, wherein the automatic wait cycles are based at least in part on a ratio between a serial clock and a system clock frequency, and a frequency of the serial clock is different from a frequency of the system clock.

2. The system of claim 1 wherein the first device is a first integrated circuit chip and the second device is a second integrated circuit chip.

3. The system of claim 1 wherein the peripheral provided on the second device is a master operative to read and write information from and to a slave of the system.

4. The system of claim 1 wherein the peripheral provided on the second device is a slave operative to receive information from and provide information to a master of the system.

5. The system of claim 4 wherein the slave is an Advanced High-performance Bus (AHB) slave that communicates via an AHB protocol.

6. The system of claim 4 wherein the slave is an Advanced Peripheral Bus (APB) slave that communicates via an APB protocol.

7. The system of claim 6 further comprising an AHBIAPB bridge provided on the first device, the AHBIAPB bridge being enhanced to permit the wait cycles in communications over the communication bus to allow the serialization of the information.

8. The system of claim 1 wherein the mechanism is configured such that the wait cycles decrease when the ratio increases.

9. The system of claim 1 further comprising at least one additional device including a peripheral, wherein a serializer coupled to the matrix is provided on the first device and is connected to a serializer on the additional device by a communication bus, the serializer on the additional device being coupled to the peripheral.

10. A method for providing bus communication, the method comprising:

serializing bus information received from a matrix using a first serializer provided on a first device and sending the serialized bus information over a communication bus; and

receiving the serialized bus information from the communication bus and deserializing the serialized bus information using a second serializer provided on a second device, wherein the deserialized information is provided to a peripheral provided on the second device, the first and second serializers introduce automatic wait cycles in a communication protocol for the communication bus to allow serialization of the information, and the automatic wait cycles are based at least in part on a ratio between a serial clock and a system clock frequency, and a frequency of the serial clock is different from a frequency of the system clock.

11. The method of claim 10 wherein the peripheral provided on the second device is a master operative to read and write information from and to a slave of the system.

12. The method of claim 10 wherein the peripheral provided on the second device is a slave operative to receive information from and provide information to a master of the system.

13. The method of claim 12 wherein the slave is an AHB slave that communicates via an AHB protocol.

14. The method of claim 12 wherein the slave is an APB slave that communicates via an APB protocol.

15. The method of claim 14 wherein an enhanced AHBJAPB bridge provided on the first device permits the wait cycles in communications over the communication bus to allow the serialization of the information.

16. A system including bus communication, the system comprising:

a matrix operative to select destinations for information on multiple buses connected to the matrix, wherein the matrix is provided on a first chip;

a first serializer coupled to the matrix and provided on the first chip, the first serializer operative to serialize information received from the matrix and send the serialized information over a communication bus;

a second serializer provided on a second chip and coupled to the communication bus, the second serializer operative to receive the serialized information and deserialize the serialized information; and

a peripheral coupled to the second serializer and provided on the second chip, wherein the peripheral receives the deserialized information from the second serializer, wherein the first and second serializers are operative to introduce automatic wait cycles in a communication protocol for the communication bus to allow for serialization of the information, and the automatic wait cycles are based at least in part on a ratio between a serial clock and a system clock frequency, and a frequency of the serial clock is different from a frequency of the system clock.

17. The system of claim 16 wherein the peripheral is a master operative to read and write information from and to a slave of the system.

18. The system of claim 16 wherein the peripheral is a slave operative to receive information from and provide information to a master of the system.

19. The system of claim 18 wherein the slave is an AHB slave that communicates via an AHB protocol.

20. The system of claim 18 wherein the slave is an APB slave that communicates via an APB protocol, and further comprising an AHBIAPB bridge provided on the first device, the AHBIAPB bridge being enhanced to permit wait cycles in communications over the communication bus to allow the serialization of the information.

21. A computer readable medium including program instructions stored in the computer readable medium to be executed by a computer and for providing bus communication, the program instructions for:

serializing bus information received from a matrix using a first serializer provided on a first device and sending the serialized bus information over a communication bus; and

receiving the serialized bus information from the communication bus and deserializing the serialized bus information using a second serializer provided on a second device, wherein the deserialized information is provided to a peripheral provided on the second device, the first and second serializers introduce automatic wait cycles in a communication protocol for the communication bus to allow serialization of the information, and the automatic wait cycles are based at least in part on a ratio between a serial clock and a system clock frequency, and a frequency of the serial clock is different from a frequency of the system clock.