Method and system for topography-aware reticle enhancement
First Claim
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1. A computer implemented method for reticle enhancement during manufacturing of an integrated circuit (IC), the method comprising the steps of:
- estimating post-planarization topography of a wafer layer of an IC using a processor of the computer, wherein the estimated post-planarization topography provides values of thickness variations in the wafer layer, the values of thickness variations defining different focus values on each of a plurality of defocus marking layers within the wafer layer;
performing reticle enhancement technique (RET) calculations based on the values of thickness variations in each defocus marking layer of the wafer layer provided by the estimated post-planarization topography of the wafer layer to derive a correction; and
incorporating the corrections resulting from the reticle enhancement technique calculations to a layout for a photomask used to transfer a pattern to the wafer layer.
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Abstract
The present invention provides a method and system for improving reticle enhancement calculations during manufacture of an integrated circuit (IC). The reticle enhancement calculations are improved by incorporating post-planarization topography estimates. A planarization process of a wafer layer is simulated to estimate the post-planarization topography. RET calculations, such as sub-resolution assist feature insertion, optical proximity corrections and phase shifting are then performed based on the post-planarization topography of the wafer layer.
27 Citations
18 Claims
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1. A computer implemented method for reticle enhancement during manufacturing of an integrated circuit (IC), the method comprising the steps of:
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estimating post-planarization topography of a wafer layer of an IC using a processor of the computer, wherein the estimated post-planarization topography provides values of thickness variations in the wafer layer, the values of thickness variations defining different focus values on each of a plurality of defocus marking layers within the wafer layer; performing reticle enhancement technique (RET) calculations based on the values of thickness variations in each defocus marking layer of the wafer layer provided by the estimated post-planarization topography of the wafer layer to derive a correction; and incorporating the corrections resulting from the reticle enhancement technique calculations to a layout for a photomask used to transfer a pattern to the wafer layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A system for reticle enhancement during manufacturing of an integrated circuit (IC), the system comprising:
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a simulator, the simulator generating an estimated post-planarization topography of a wafer layer on the IC, wherein the estimated post-planarization topography provides values of thickness variations in the wafer layer, the values of thickness variations defining different focus values at each of a plurality of defocus marking layers within the wafer layer; and a calculation module, the calculation module performing reticle enhancement technique (RET) calculations based on the values of thickness variations on each of the defocus marking layer in the wafer layer provided by the estimated post-planarization topography of the wafer layer to derive a correction, wherein the RET calculations are used to incorporate corrections for a layout of a photomask used to transfer a pattern to the wafer layer. - View Dependent Claims (12, 13, 14)
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15. A computer program product for use with a computer, the computer program product comprising a computer storage device usable medium having a computer readable program code embodied therein for reticle enhancement during manufacturing of an integrated circuit (IC), the computer readable program code performing the steps of:
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estimating a post-planarization topography of a wafer layer on the IC, wherein the estimated post-planarization topography provides values of thickness variations in the wafer layer, the values of thickness variations defining different focus values on each of a plurality of defocus marking layers within the wafer layer; performing reticle enhancement technique (RET) calculations based on the values of thickness variations on each defocus marking layer in the wafer layer provided by the estimated post-planarization topography of the wafer layer to derive a correction; and incorporating the corrections resulting from the reticle enhancement technique calculations to a layout for a photomask used to transfer a pattern to the wafer layer. - View Dependent Claims (16, 17, 18)
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Specification