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Method and system for topography-aware reticle enhancement

  • US 7,814,456 B2
  • Filed: 11/04/2005
  • Issued: 10/12/2010
  • Est. Priority Date: 11/22/2004
  • Status: Expired due to Fees
First Claim
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1. A computer implemented method for reticle enhancement during manufacturing of an integrated circuit (IC), the method comprising the steps of:

  • estimating post-planarization topography of a wafer layer of an IC using a processor of the computer, wherein the estimated post-planarization topography provides values of thickness variations in the wafer layer, the values of thickness variations defining different focus values on each of a plurality of defocus marking layers within the wafer layer;

    performing reticle enhancement technique (RET) calculations based on the values of thickness variations in each defocus marking layer of the wafer layer provided by the estimated post-planarization topography of the wafer layer to derive a correction; and

    incorporating the corrections resulting from the reticle enhancement technique calculations to a layout for a photomask used to transfer a pattern to the wafer layer.

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