Vertically stacked field programmable nonvolatile memory and method of fabrication
First Claim
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1. A process for fabricating a 3-D semiconductor memory device comprising the steps of:
- forming a first stack comprising a steering element and a state change element;
forming a second stack comprising a steering element and a state change element overlying the first stack, wherein the first and second stacks comprise elements of a pillar in a 3-D memory array; and
forming an oxide layer on an edge of the pillar to passivate any edge traps.
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Abstract
A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
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20 Claims
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1. A process for fabricating a 3-D semiconductor memory device comprising the steps of:
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forming a first stack comprising a steering element and a state change element; forming a second stack comprising a steering element and a state change element overlying the first stack, wherein the first and second stacks comprise elements of a pillar in a 3-D memory array; and forming an oxide layer on an edge of the pillar to passivate any edge traps. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A process for fabricating a pillar in a 3-D semiconductor memory device, wherein the pillar includes a steering element and a state change element vertically arranged between orthogonally disposed conductors leads, the process comprising the steps of:
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forming a semiconductor layer; and oxidizing at least a portion of the semiconductor layer in a plasma to form an oxide antifuse layer overlying the semiconductor layer; wherein the 3-D semiconductor memory device comprises a plurality of layers of memory cells stacked vertically above one another. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A process for forming a 3-D semiconductor memory device, the process comprising:
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forming a first stack comprising a steering element and a state change element; forming a second stack comprising a steering element and a state change element overlying the first stack, wherein the first and second stacks comprise elements of a pillar in a 3-D memory array; and forming a self-limiting oxide layer on an edge of the pillar to reduce leakage current in the memory device. - View Dependent Claims (17, 18, 19, 20)
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Specification