Method for producing a trench transistor and trench transistor

• US 7,816,210 B2
• Filed: 08/30/2006
• Issued: 10/19/2010
• Est. Priority Date: 08/30/2005
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Hirler, Franz, Poelzl, Martin
• Primary Examiner(s): Pham; Thanh V
• Assistant Examiner(s): Ligai; Maria
• Application Number:
  US11/512,749
• Publication Number:
  US 20070059887A1
• Time in Patent Office: 1,511 Days
• Field of Search: 438/271, 438/272, 438/259, 438/589, 438/258, 438/212, 257/302, 257/331, 257/332, 257/E29.26, 257/E29.257, 257/E29.262
• US Class Current: 438/271
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method is disclosed for producing a trench transistor which has at least two trenches with in each case a field electrode arranged therein and a gate electrode arranged therein. In the method, it is provided to implement the trenches with different trench widths and then to produce the field electrodes by filling up the trenches with an electrode material and subsequent cutting back of the electrode material. The different trench width leads to different etching rates during the cutting back of the electrode material, and thus to field electrodes which are spaced apart from a top edge of the trenches by different amounts. Following this, the gate electrodes are produced which, due to the different dimensions of the field electrodes, extend into the trenches to a different depth, resulting in different gate capacitances for the gate electrodes in the two trenches.

Claims

1. A method for producing a trench transistor, the method comprising:

providing a semiconductor body including a first side and a second side;

producing at least one first trench and at least one second trench, the at least one first trench and at least one second trench arranged spaced apart from one another and extending into the semiconductor body starting from the first side of the semiconductor body;

applying a first dielectric layer to exposed surfaces of the at least one first trench and the at least one second trench;

filling the at least one first trench and the at least one second trench up to the same height with an electrode material;

partially removing the electrode material from the at least one first trench and the at least one second trench by applying an etching process in which an etching agent acts on the electrode material for a predetermined etching period, the etching process resulting in a first field electrode in the at least one first trench and a second field electrode in the at least one second trench; and

producing a first gate electrode in the at least one first trench above the first field electrode and a second gate electrode in the at least one second trench above the second field electrode, the first gate electrode and the second gate electrode insulated from the semiconductor body by a gate dielectric layer;

wherein the at least one first trench defines a first trench width in a lateral direction of the semiconductor body, and wherein the at least one second trench defines a second trench width in the lateral direction of the semiconductor body, the first trench width wider than the second trench width such that, during the etching process, the electrode material in the at least one first trench is etched deeper relative to the first side of the semiconductor body than in the at least one second trench.

2. The method of claim 1 wherein the at least one first trench comprises a number of first trenches and the at least one second trench comprises a number of second trenches, wherein the ratio between the number of first trenches and the number of second trenches is between 1:

1 and 4;

1.

3. The method of claim 1 further comprising the step of producing at least one third trench which joins the first and second trenches.

4. The method of claim 1 wherein the first gate electrode and second gate electrode are produced in such a manner that they are arranged dielectrically insulated from the first field electrode and the second field electrode.

5. The method as claimed in one of the preceding claims, in which the gate electrodes in the first and second trenches are produced in such a manner that they are electrically conductively connected to the first and second field electrodes.

6. The method as claimed in claim 1, wherein the at least one first trench and the at least one second trench comprise a plurality of adjacent trenches, wherein the distances between adjacent trenches are in each case of equal magnitude.

7. The method of claim 1 wherein the semiconductor body includes a doped first semiconductor layer and a doped second semiconductor layer, wherein the second semiconductor layer is doped more lightly than the first semiconductor layer, and wherein the at least one first trench and the at least one second trench are produced in the second semiconductor layer.

8. The method of claim 7 wherein a semiconductor zone with complementary doping to the second semiconductor layer is produced adjacent to the first gate electrode and the second gate electrode.

9. The method of claim 1 wherein the etching process is a plasma etching process.