Method of manufacturing composite wafer structure

• US 7,816,233 B2
• Filed: 10/07/2005
• Issued: 10/19/2010
• Est. Priority Date: 07/22/2005
• Status: Active Grant

• Current Assignee: Sino-American Silicon Products Incorporated
• Original Assignee: Sino-American Silicon Products Incorporated
• Inventors: Hsu, Wen-Ching, Ho, Ya-Lan, Wang, Jung-Tsung, Hsu, Sung-Lin, Huang, Jing-Yi, Yeh, Jer-Liang
• Primary Examiner(s): Richards; N Drew
• Assistant Examiner(s): Garcia; Joannie A
• Application Number:
  US11/245,163
• Publication Number:
  US 20070020873A1
• Time in Patent Office: 1,838 Days
• Field of Search: 438/113, 438/406, 438/455, 438/458, 438/459, 438/FOR.386
• US Class Current: 438/458
• CPC Class Codes: H01L 21/76256 using silicon etch back techniques, e.g. BESOI, ELTRAN

Abstract

The invention provides a method of manufacturing a composite wafer structure. In particular, the method, according to the invention, is based on the fracture mechanics theory to actively control fracture induced during the manufacture of the composite wafer structure and to further protect from undesired edge damage. Thereby, the method, according to the invention, can enhance the yield rate of industrial mass production regarding the composite wafer structure.

Claims

1. A method of manufacturing a composite wafer structure, comprising the steps of:

(a) preparing a device wafer having a first circumference, a bond surface and a bottom surface;

(b) forming a groove on the bond surface along the first circumference of the device wafer, wherein a margin exists between the groove and the first circumference of the device wafer;

(c) preparing a base wafer having a top surface;

(d) bonding the bond surface of the device wafer onto the top surface of the base wafer; and

(e) grinding and polishing the bottom surface of the device wafer until an initial thickness of the device wafer is reduced into an expected thickness to complete the composite wafer structure;

wherein during the grinding and polishing of the bottom surface of the device wafer, the margin is fractured by cracks induced at a tip of the groove and then removed;

wherein the base wafer has a second circumference, after step (d), in which a maximum radial distance on the bond surface of the device not bonded with the top surface of the base wafer is defined as a mismatch gap, and a thickness of the margin is equal to or larger than the mismatch gap;

wherein the second circumference of the base wafer is ground or laser cut until a diameter of the base wafer is reduced to be equal to that of the device wafer; and

wherein the device wafer and the base wafer are respectively formed of a semiconductor material of a first type and a second type.

2. The method of claim 1, between step (d) and step (e), further comprising the step of:

performing an annealing treatment to enhance a bonding strength between the device wafer and the base wafer.

3. The method of claim 2, wherein in step (d), before the bond surface of the device wafer is bonded onto the top surface of the base wafer, a plasma treatment is applied on the bond surface of the device wafer and the top surface of the base wafer.

4. The method of claim 1, wherein the groove is formed by a mechanical process, a laser cutting process, an etching process, or a water-jet cutting process.

5. The method of claim 1, between step (c) and step (d), further comprising the step of:

performing an oxidized layer on the bond surface of the device wafer and/or on the top surface of the base wafer.

6. The method of claim 5, wherein the first type semiconductor material is a silicon material.

7. The method of claim 1, wherein the second type semiconductor material is different from the first type semiconductor material.

8. The method of claim 7, wherein the second type semiconductor material is a silicon material, and the first type semiconductor material is one selected from the group consisting of a SiGe material, a LiNbO₃ material, a sapphire material, and an oxide material.

9. A method of manufacturing a composite wafer structure, comprising the steps of:

(a) preparing a device wafer having a first circumference, a bond surface, and a bottom surface;

(b) performing a hydrogen ion implantation process for the bond surface of the device wafer at a region along the first circumference and with a margin apart from the first circumference, such that at the region, hydrogen ions are implanted in the device wafer from near the bond surface to a predetermined depth underneath the bond surface;

(c) preparing a base wafer having a top surface;

(d) bonding the bond surface of the device wafer onto the top surface of the base wafer;

(e) performing an annealing treatment to aggregate the implanted hydrogen ions into micro voids distributed in the device wafer from near the bond surface to the predetermined depth underneath the bond surface; and

(f) grinding and polishing the bottom surface of the device wafer until an initial thickness of the device wafer is reduced into an expected thickness to complete the composite wafer structure;

wherein during the grinding and polishing of the bottom surface of the device wafer, the margin is fractured by the micro voids and then removed;

wherein the base wafer has a second circumference, after the step of bonding the bonding surface of the device wafer onto the top surface of the base wafer, a maximum radial distance on the bond surface of the device not bonded with the top surface of the base wafer is defined as a mismatch gap, and a thickness of the margin is equal to or larger than the mismatch gap; and

wherein the second circumference of the base wafer is ground or laser cut until a diameter of the base wafer is reduced to be equal to that of the device wafer; and

wherein the device wafer and the base wafer are formed of a semiconductor material of a first type and a second type.

10. The method of claim 9, wherein in step (d), before the bond surface of the device wafer is bonded onto the top surface of the base wafer, a plasma treatment is applied on the bond surface of the device wafer and the top surface of the base wafer.

11. The method of claim 9, between step (c) and step (d), further comprising the step of:

forming an oxidized layer on the bond surface of the device wafer and/or on the top surface of the base wafer.

12. The method of claim 11, wherein the first type semiconductor material is a silicon material.

13. The method of claim 9, wherein the second type semiconductor material is different from the first type semiconductor material.

14. The method of claim 13, wherein the second type semiconductor material is a silicon material, and the first type semiconductor material is one selected from the group consisting of a SiGe material, a LiNbO₃ material, a sapphire material, and an oxide material.

15. A method of manufacturing a composite wafer structure, comprising the steps of:

(a) preparing a device wafer having a first circumference, a bond surface and a bottom surface;

(b) forming a groove on the bond surface along the first circumference of the device wafer, wherein a margin exists between the groove and the first circumference of the device wafer;

(c) preparing a base wafer having a top surface;

(d) bonding the bond surface of the device wafer onto the top surface of the base wafer; and

(e) grinding and polishing the bottom surface of the device wafer until an initial thickness of the device wafer is reduced into a thickness to complete the composite wafer structure;

wherein during the grinding and polishing of the bottom surface of the device wafer, the margin is fractured by cracks induced at a tip of the groove and then removed; and

wherein the device wafer is formed of a first semiconductor material, and the base wafer is formed of a second semiconductor material different from the first semiconductor material.

16. The method of claim 15, wherein the base wafer has a second circumference, after step (d), in which a maximum radial distance on the bond surface of the device wafer not bonded with the top surface of the base wafer is defined as a mismatch gap, and a thickness of the margin is equal to or larger than the mismatch gap.

17. The method of claim 16, further comprising the step of:

grinding or laser cutting the second circumference of the base wafer until a diameter of the base wafer is reduced to be equal to that of the device wafer.

18. The method of claim 15, between step (d) and step (e), further comprising the step of:

performing an annealing treatment to enhance a bonding strength between the device wafer and the base wafer.

19. The method claim 18, wherein in step (d), before the bond surface of the device wafer is bonded onto the top surface of the base wafer, a plasma treatment is applied on the bond surface of the device wafer and the top surface of the base wafer.

20. The method of claim 15, wherein the groove is formed by a mechanical process, a laser cutting process, an etching process, or a water-jet cutting process.

21. The method of claim 15, between step (c) and step (d), further comprising the step of:

forming an oxidized layer on the bond surface of the device wafer and/or on the top surface of the base wafer.

22. The method of claim 21, wherein the first semiconductor material is a silicon material.

23. The method of claim 15, wherein the second semiconductor material is a silicon material, and the first semiconductor material is one selected from the group consisting of a SiGe material, a LiNbO₃ material, a sapphire material, and an oxide material.

24. A method of manufacturing a composite wafer structure, comprising the steps of:

(a) preparing a device wafer having a first circumference, a bond surface and a bottom surface;

(b) forming a hydrogen ion implantation process for the bond surface of the device wafer at a region along the first circumference and with a margin apart from the first circumference, such that at the region, hydrogen ions are implanted in the device wafer from near the bond surface to a depth underneath the bond surface;

(c) preparing a base wafer having a top surface;

(d) bonding the bond surface of the device wafer onto the top surface of the base wafer;

(e) performing an annealing treatment to aggregate the implanted hydrogen ions into micro voids distributed in the device wafer from near the bond surface to the depth underneath the bond surface; and

(f) grinding and polishing the bottom surface of the device wafer until an initial thickness of the device wafer is reduced into a thickness to complete the composite wafer structure;

wherein during the grinding and polishing of the bottom surface of the device wafer, the margin is fractured by cracks induced at a tip of the groove and then removed; and

wherein the device wafer is formed of a first semiconductor material, and the base wafer is formed of a second semiconductor material different from the first semiconductor material; and

wherein the second semiconductor material is a silicon material, and the first semiconductor material is one selected from the group consisting of a SiGe material, a LiNbO₃ material, a sapphire material, and an oxide material.

25. The method of claim 24, wherein the base wafer has a second circumference, after the step of bonding the bond surface of the device wafer onto the top surface of the base wafer, in which a maximum radial distance on the bond surface of the device wafer not bonded with the top surface of the base wafer is defined as a mismatch gap, and a thickness of the margin is equal to or larger than the mismatch gap.

26. The method of claim 25, further comprising the step of:

grinding or laser cutting the second circumference of the base wafer until a diameter of the base wafer is reduced to be equal to that of the device wafer.

27. The method claim 24, wherein in step (d), before the bond surface of the device wafer is bonded onto the top surface of the base wafer, a plasma treatment is applied on the bond surface of the device wafer and the top surface of the base wafer.

28. The method of claim 24, between step (c) and step (d), further comprising the step of:

forming an oxidized layer on the bond surface of the device wafer and/or on the top surface of the base wafer.