Memory array

• US 7,816,722 B2
• Filed: 02/04/2004
• Issued: 10/19/2010
• Est. Priority Date: 02/04/2004
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Jackson, Warren B., Van Brocklin, Andrew L., Fricke, Peter J.
• Primary Examiner(s): Nadav; Ori
• Application Number:
  US10/772,945
• Publication Number:
  US 20050167787A1
• Time in Patent Office: 2,449 Days
• Field of Search: 257/202, 257/209, 257/211, 257/390, 257314-326, 257/635, 257/645, 257/646, 257/651
• US Class Current: 257/314
• CPC Class Codes: H01L 27/101 including resistors or capacitors only

Abstract

A memory array has a multiplicity of row conductors and a multiplicity of column conductors, the row conductors and column conductors being arranged to cross at cross-points, and has a memory cell disposed at each cross-point, each memory cell having a storage element and a control element coupled in series between a row conductor and a column conductor, and each control element including a silicon-rich insulator. Methods for fabricating the memory array are disclosed.

Claims

1. A memory array comprising:

a) a multiplicity of row conductors and a multiplicity of column conductors, the row conductors and column conductors being arranged to cross at cross-points, and

b) a memory cell disposed at each cross-point, each memory cell having exactly two terminals and having a storage element and a control element coupled in series between a row conductor and a column conductor, each storage element comprising a low-resistance filament disposed therein, each control element including a tunnel junction and a silicon-rich insulator, wherein the low-resistance filament of the storage element electrically interconnects the silicon-rich insulator with one of the row conductor and the column conductor, and wherein the silicon-rich insulator injects current into the tunnel junction when the memory cell is selected.

2. The memory array of claim 1, wherein the silicon-rich insulator of each memory cell is patterned.

3. The memory array of claim 1, wherein the silicon-rich insulator of each memory cell comprises silicon-rich oxide (SRO).

4. The memory array of claim 1, wherein the silicon-rich insulator of each memory cell is electrically isolated from the silicon-rich insulators of all other memory cells.

5. The memory array of claim 1, wherein the control element of each memory cell further comprises a tunnel junction thickness of about 3-5 nanometers.

6. The memory array of claim 1, wherein the storage element of each memory cell comprises an anti-fuse.

7. The memory array of claim 1, wherein the storage element of each memory cell comprises a tunnel junction.

8. The memory array of claim 1, wherein the storage element of each memory cell comprises a state-change layer.

9. The memory array of claim 8, wherein the state-change layer of the storage element comprises a chalcogenide.

10. The memory array of claim 1, wherein the row conductors are arranged in mutually orthogonal relationship with the column conductors.

11. The memory array of claim 1, wherein the two terminals of the two-terminal memory cell disposed at each cross-point comprise the row conductor and column conductor respectively.

12. A memory array comprising:

a) a multiplicity of row conductors and a multiplicity of column conductors, the row conductors and column conductors being arranged to cross at cross-points, and

b) a memory cell disposed at each cross-point, each memory cell having exactly two terminals, each memory cell comprising means for storing data and means for controlling the means for storing data, the means for storing data and means for controlling being coupled in series between a row conductor and a column conductor, each means for storing data comprising a low-resistance filament disposed therein, each means for controlling including a tunnel junction and a silicon-rich insulator, wherein the low-resistance filament of the storage element electrically interconnects the silicon-rich insulator with one of the row conductor and the column conductor, and wherein the silicon-rich insulator injects current into the tunnel junction when the memory cell is selected.

13. The memory array of claim 12, wherein the two terminals of the two-terminal memory cell disposed at each cross-point comprise the row conductor and column conductor respectively.

14. A memory cell made by a method comprising:

a) providing a substrate,

b) depositing and patterning a first conductive layer over the substrate,

c) forming a storage layer over the patterned first conductive layer, the storage layer comprising a low-resistance filament disposed therein,

d) forming a layer of silicon-rich insulator over the storage layer,

e) forming a tunnel-junction layer over the layer of silicon-rich insulator, and

f) forming and patterning a second conductive layer over the tunnel-junction layer, whereby a memory-cell stack is formed, the stack having a storage layer, a silicon-rich insulator, and a tunnel-junction layer in series relationship between the first and second conductive layers, such that the first and second conductive layers are adapted to provide exactly two terminals for control of the memory cell, wherein the low-resistance filament of the storage layer electrically interconnects the layer of silicon-rich insulator with the first conductive layer, and wherein the silicon-rich insulator injects current into the tunnel-junction layer when the memory cell is selected.

15. A memory array comprising a multiplicity of memory cells made by the method of claim 14.

16. A substrate carrying electronics comprising the memory array of claim 15.

17. An integrated circuit comprising the memory array of claim 15.

18. A multilayer memory comprising:

a) a multiplicity of the memory arrays of claim 15, arranged in memory layers,

b) a multiplicity of interlayer dielectrics disposed to separate adjacent memory layers, and

c) conductive vias selectively extending through the interlayer dielectrics to selectively interconnect memory cells of the memory arrays.

19. A substrate carrying electronics comprising the multilayer memory of claim 18.

20. An integrated circuit comprising the multilayer memory of claim 18.

21. The multilayer memory of claim 18, wherein the memory cells of the multilayer memory are organized in sets, the memory cells of each set being disposed to overlay vertically at least a portion of an adjacent set, whereby some portion of the memory cells of each set are aligned vertically with each other.

22. A memory cell made by a method comprising:

a) providing a substrate,

b) depositing and patterning a first conductive layer over the substrate,

c) forming a storage layer over the patterned first conductive layer, said storage layer comprising a low-resistance filament disposed therein,

d) forming a layer of silicon-rich insulator over the storage layer,

e) forming a tunnel-junction layer over the layer of silicon-rich insulator,

f) forming and patterning a second conductive layer over the tunnel-junction layer,

g) forming and patterning an interlayer dielectric over the storage layer,

h) forming an opening through the interlayer dielectric and extending to the storage layer, and

i) filling the opening through the interlayer dielectric with conductive material to form a middle electrode contiguous with the storage layer, wherein the first and second conductive layers are adapted to provide exactly two terminals for control of the memory cell, and wherein the low-resistance filament of the storage layer electrically interconnects the silicon-rich insulator with the first conductive layer, and wherein the silicon-rich insulator injects current into the tunnel-junction layer when the memory cell is selected.

23. A memory array comprising a multiplicity of memory cells made by the method of claim 22.

24. A substrate carrying electronics comprising the memory array of claim 23.

25. An integrated circuit comprising the memory array of claim 23.

26. A multilayer memory made by a method comprising:

a) providing a substrate,

b) depositing and patterning a first conductive layer over the substrate,

c) forming a storage layer over the patterned first conductive layer, said storage layer comprising a low-resistance filament disposed therein,

d) forming and patterning a first interlayer dielectric over the storage layer,

e) forming an opening through the first interlayer dielectric and extending to the storage layer,

f) filling the opening through the first interlayer dielectric with conductive material to form a middle electrode, said middle electrode being electrically coupled to said first conductive layer through said low-resistance filament of said storage layer,

g) forming a layer of silicon-rich insulator over at least the first interlayer dielectric, at least a portion of the silicon-rich insulator being disposed contiguous with the middle electrode,

h) forming a tunnel-junction layer over the layer of silicon-rich insulator,

i) forming and patterning a second conductive layer over the tunnel-junction layer and disposed to overlay vertically at least a portion of the middle electrode, whereby a portion of the second conductive layer is aligned with some portion of the middle electrode, and wherein the first and second conductive layers are adapted to provide exactly two terminals for control of a memory cell, and wherein the silicon-rich insulator injects current into the tunnel-junction layer when the memory cell is selected,

j) forming and patterning a second interlayer dielectric over the patterned second conductive layer, whereby a substrate is formed for subsequent layers,

k) forming vias as required through the second interlayer dielectric, and

l) repeating steps b) through k) until a desired number of memory array layers have been formed.

27. A substrate carrying electronics comprising the multilayer memory made by the method of claim 26.

28. An integrated circuit comprising the multilayer memory made by the method of claim 26.

29. A multilayer memory made by a method comprising:

a) providing a substrate,

b) depositing and patterning a first conductive layer over the substrate,

c) forming a tunnel-junction layer over the first conductive layer,

d) forming a layer of silicon-rich insulator over the tunnel-junction layer,

e) forming and patterning a first interlayer dielectric over the layer of silicon-rich insulator,

f) forming an opening through the first interlayer dielectric and extending to the layer of silicon-rich insulator,

g) filling the opening through the first interlayer dielectric with conductive material to form a middle electrode, at least a portion of the middle electrode being disposed contiguous with the silicon-rich insulator,

h) forming a storage-element layer over the patterned first interlayer dielectric, said storage-element layer comprising a low-resistance filament disposed therein,

i) forming and patterning a second conductive layer over the storage-element layer, the patterned second conductive layer being disposed to overlay vertically at least a portion of the middle electrode, such that a portion of the second conductive layer is aligned with some portion of the middle electrode, wherein the low-resistance filament of the storage element electrically interconnects the layer of silicon-rich insulator with the middle electrode, and wherein the first and second conductive layers are adapted to provide exactly two terminals for control of a memory cell, and wherein the silicon-rich insulator injects current into the tunnel-junction layer when the memory cell is selected,

j) forming and patterning a second interlayer dielectric over the patterned second conductive layer, whereby a substrate is formed for subsequent layers,

k) forming vias as required through the second interlayer dielectric, and

l) repeating steps b) through k) until a desired number of memory array layers have been formed.

30. A substrate carrying electronics comprising the multilayer memory made by the method of claim 29.

31. An integrated circuit comprising the multilayer memory made by the method of claim 29.