Semiconductor device and method for fabricating the same

• US 7,816,730 B2
• Filed: 08/28/2007
• Issued: 10/19/2010
• Est. Priority Date: 04/12/2007
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Lee, Sang Don
• Primary Examiner(s): Louie; Wai-Sing
• Assistant Examiner(s): TANG, SUIAN
• Application Number:
  US11/846,509
• Publication Number:
  US 20080251839A1
• Time in Patent Office: 1,148 Days
• Field of Search: 257/331, 257/E21, 257/E29, 438/268, 438/157, 438/164, 438/283, 438/525
• US Class Current: 257/331
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/7854 with rounded corners

Abstract

A semiconductor device comprises a fin-type active region defined by a semiconductor substrate having a device isolation structure, a recess formed over the fin-type active region, and a gate electrode including a silicon germanium (Si_1-xGe_x) layer for fill the recess (where 0<X<1 and X is a Ge mole fraction).

Claims

1. A method for fabricating a semiconductor device, the method comprising:

forming a device isolation structure on a semiconductor substrate to define an active region;

selectively etching a portion of the device isolation structure to form a fin-type active region;

forming a gate structure over the fin-type active region, the gate structure including a silicon germanium layer formed over a polysilicon layer; and

performing a thermal treatment on the semiconductor substrate to drive dopants of the silicon germanium layer into the polysilicon layer such that the silicon germanium layer expands into the polysilicon layer.

2. The method of claim 1, wherein the step of forming the fin-type active region comprises:

forming a hard mask layer over the semiconductor substrate;

forming a photoresist pattern over the hard mask layer to define a recess gate region;

selectively etching the hard mask layer and the device isolation structure by using the photoresist pattern as an etching mask to form a recess exposing the fin-type active region; and

removing the photoresist pattern and the hard mask layer to expose the active region including the fin-type active region.

3. The method of claim 1, further comprising performing a soft etching process on the fin-type active region.

4. The method of claim 1, wherein the step of forming the gate structure comprises:

forming a lower gate conductive layer including the silicon germanium layer and the polysilicon layer over the semiconductor substrate;

forming an upper gate conductive layer and a gate hard mask layer over the lower gate conductive layer; and

patterning the gate hard mask layer, the upper gate conductive layer, and the lower gate conductive layer to form the gate structure.

5. The method of claim 4, wherein the polysilicon layer comprises a first p+ layer and a second p+ layer, and the silicon germanium layer comprises a p+ polysilicon layer, the step of forming the lower gate conductive layer comprising:

forming the first p+ polysilicon layer over the semiconductor substrate;

forming the p+ polysilicon germanium layer over the first p+ polysilicon layer; and

forming the second p+ polysilicon layer over the p+ polysilicon germanium layer,

wherein the step of performing the thermal treatment process on the semiconductor substrate forms a stacked structure of the p+ polysilicon layer and the p+ polysilicon germanium layer.

6. The method of claim 1, further comprising forming a gate insulating film over the active region including the fin-type active region.

7. The method of claim 1, further comprising forming a LDD region on the semiconductor substrate at both sides of the gate structure.

8. The method of claim 7, wherein a thickness of the silicon germanium layer is at least equal to a depth of the LDD region.

9. A method for fabricating a semiconductor device, the method comprising:

forming a device isolation structure on a semiconductor substrate to define an active region;

etching a portion of the device isolation structure to form a fin-type active region; and

forming a gate structure over the fin-type active region, the gate structure including a polysilicon layer, a doped polysilicon layer over the polysilicon layer, and a gate conductive layer over the doped polysilicon layer, the gate conductive layer including metal,

wherein the doped polysilicon layer is a silicon germanium defined as Si_1-xGe_x, where 0<

X<

1 and X is a Ge mole fraction,

wherein a lower surface of the doped polysilicon layer is provided below an upper surface of the fin-type active region.

10. The method of claim 9, wherein the doped polysilicon is formed by implanting dopants into the polysilicon layer and preforming a thermal treatment of the substrate.