Systems and methods for integrated circuits comprising multiple body biasing domains

• US 7,816,742 B1
• Filed: 04/06/2006
• Issued: 10/19/2010
• Est. Priority Date: 09/30/2004
• Status: Active Grant

• Current Assignee: Meta Platforms, Inc. (f/k/a Facebook, Inc.)
• Original Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Inventors: Koniaris, Kleanthes G., Burr, James B., Masleid, Robert Paul
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US11/400,368
• Time in Patent Office: 1,657 Days
• Field of Search: 257/371, 257/401, 257/544, 327/534
• US Class Current: 257/371
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

Systems and methods for integrated circuits comprising multiple body biasing domains. In accordance with a first embodiment of the present invention, a semiconductor structure comprises a substrate of first type material. A first closed structure comprising walls of second type material extends from a surface of the substrate to a first depth. A planar deep well of said second type material underlying and coupled to the closed structure extends from the first depth to a second depth. The closed structure and the planar deep well of said second type material form an electrically isolated region of the first type material. A second-type semiconductor device is disposed to receive a first body biasing voltage from the electrically isolated region of the first type material. A well of the second-type material within the electrically isolated region of the first type material is formed and a first-type semiconductor device is disposed to receive a second body biasing voltage from the well of second-type material.

Claims

1. An integrated circuit including:

a first plurality of n-type active devices configured to accept a first n-type body biasing voltage;

a first plurality of p-type active devices configured to accept a first p-type body biasing voltage;

a second plurality of n-type active devices configured to accept a second n-type body biasing voltage;

a second plurality of p-type active devices configured to accept a second p-type body biasing voltage;

wherein the body terminals of the first plurality of n-type active devices and the body terminals of the first plurality of p-type active devices and the body terminals of the second plurality of n-type active devices and the body terminals of the second plurality of p-type active devices are configured to be electrically isolated from one another;

wherein the first plurality of n-type active devices and the first plurality of p-type active devices are operable to operate at an increased frequency in response to the first plurality of n-type active devices and the first plurality of p-type active devices receiving body bias compared to an unbiased condition; and

wherein the second plurality of n-type active devices and the second plurality of p-type active devices are operable to operate at a decreased upper frequency limit in response to the second plurality of n-type active devices and the second plurality of p-type active devices receiving body bias compared to an unbiased condition.

2. The integrated circuit of claim 1 wherein:

the first plurality of n-type active devices and the first plurality of p-type active devices are configured to accept the first n-type body biasing voltage and the first p-type body biasing voltage, respectively, resulting in a decreased leakage current for the first plurality of n-type active devices and the first plurality of p-type active devices compared to an unbiased condition.

3. The integrated circuit of claim 2 wherein:

the first plurality of n-type active devices and the first plurality of p-type active devices are configured to accept the first n-type body biasing voltage and the first p-type body biasing voltage to the first plurality of n-type active devices and the first plurality of p-type active devices, respectively, resulting in the first plurality of n-type active devices and the first plurality of p-type active devices being unable to perform a designed function.

4. The integrated circuit of claim 3 wherein the first plurality of n-type active devices and the first plurality of p-type active devices are configured to perform the designed function in an unbiased condition.

5. The integrated circuit according to claim 1 wherein:

as fabricated, the first plurality of n-type active devices and the first plurality of p-type active devices are unable to perform a designed function in an unbiased condition; and

the first plurality of n-type active devices and the first plurality of p-type active devices are able to perform the designed function when biased by the first n-type body biasing voltage and the first p-type body biasing voltage, respectively.

18. The integrated circuit of claim 1 wherein the second plurality of n-type active devices and the second plurality of p-type active devices are operable to perform a function as biased by the second n-type body biasing voltage and the second p-type body biasing voltage, respectively.

6. An integrated circuit comprising:

means for applying a first pair of body biasing voltages to circuitry of a first body biasing domain;

means for applying a second pair of body biasing voltages to circuitry of a second body biasing domain; and

means for performing a function characteristic of the integrated circuit, the function utilizing the circuitry of the second body biasing domain as biased by the second pair of body biasing voltages, the means for performing a function configured to be responsive to the means for applying the second pair of body biasing voltages

wherein the means for applying the first pair of body biasing voltages includes a configuration to increase a frequency of operation for the circuitry means of the first body biasing domain compared to nominal and wherein the means for applying the second pair of body biasing voltages includes a configuration to decrease an upper frequency of operation for the circuitry means of the second body biasing domain compared to nominal.

7. The integrated circuit of claim 6 wherein the means for applying the first pair of body biasing voltages decreases leakage current of the circuitry means of the first body biasing domain compared to nominal.

8. The integrated circuit of claim 7 wherein the means for applying of the first pair of body biasing voltages renders the circuitry means of the first body biasing domain unable to perform a desired function.

9. The integrated circuit of claim 8 wherein the circuitry means of the first body biasing domain performs a desired function.

10. The integrated circuit of claim 6 wherein the circuitry means of the first body biasing domain does not produce a desired function without application of the first pair of body biasing voltages.

11. An integrated circuit comprising:

a first body biasing domain comprising a first plurality of nFET and pFET devices;

a second body biasing domain comprising a second plurality of nFET and pFET devices;

wherein said first plurality of nFET and pFET devices are configured to receive a first nFET and a first pFET body biasing voltages;

wherein said second plurality of nFET and pFET devices are configured to receive a second nFET and a second pFET body biasing voltages; and

wherein said integrated circuit is configured to apply said first nFET and said first pFET body biasing voltages independent of other body biasing voltages within said integrated circuit,

wherein said first body biasing domain is operable to operate at an increased frequency responsive to said first nFET and said first pFET body biasing voltages and

said second body biasing domain is operable to operate at a decreased upper frequency limit responsive to said second nFET and second first pFET body biasing voltages.

12. The integrated circuit of claim 11 wherein said first nFET and said first pFET body biasing voltages are applied in conjunction to achieve a complementary effect on devices within said first body biasing domain.

13. The integrated circuit of claim 12 wherein said second nFET and a second pFET body biasing voltages are applied in conjunction to achieve a complementary effect on devices within said second body biasing domain.

14. The integrated circuit of claim 11 wherein said first nFET and said first pFET body biasing voltages are applied to decrease leakage current of devices within said first body biasing domain.

15. The integrated circuit of claim 11 wherein said first nFET and said first pFET body biasing voltages are applied to increase maximum operating frequency of devices within said first body biasing domain.

16. The integrated circuit of claim 15 wherein:

said first nFET and said first pFET body biasing voltages are operable to decrease leakage current of devices within said first body biasing domain until said first devices within said first body biasing domain are no longer capable of performing a desired function; and

devices within said second body biasing domain are capable of performing a desired function.

17. The integrated circuit of claim 11 in which a signal generated within said first body biasing domain is configured to be accessed within said second body biasing domain.