Systems and methods for integrated circuits comprising multiple body biasing domains
First Claim
1. An integrated circuit including:
- a first plurality of n-type active devices configured to accept a first n-type body biasing voltage;
a first plurality of p-type active devices configured to accept a first p-type body biasing voltage;
a second plurality of n-type active devices configured to accept a second n-type body biasing voltage;
a second plurality of p-type active devices configured to accept a second p-type body biasing voltage;
wherein the body terminals of the first plurality of n-type active devices and the body terminals of the first plurality of p-type active devices and the body terminals of the second plurality of n-type active devices and the body terminals of the second plurality of p-type active devices are configured to be electrically isolated from one another;
wherein the first plurality of n-type active devices and the first plurality of p-type active devices are operable to operate at an increased frequency in response to the first plurality of n-type active devices and the first plurality of p-type active devices receiving body bias compared to an unbiased condition; and
wherein the second plurality of n-type active devices and the second plurality of p-type active devices are operable to operate at a decreased upper frequency limit in response to the second plurality of n-type active devices and the second plurality of p-type active devices receiving body bias compared to an unbiased condition.
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Accused Products
Abstract
Systems and methods for integrated circuits comprising multiple body biasing domains. In accordance with a first embodiment of the present invention, a semiconductor structure comprises a substrate of first type material. A first closed structure comprising walls of second type material extends from a surface of the substrate to a first depth. A planar deep well of said second type material underlying and coupled to the closed structure extends from the first depth to a second depth. The closed structure and the planar deep well of said second type material form an electrically isolated region of the first type material. A second-type semiconductor device is disposed to receive a first body biasing voltage from the electrically isolated region of the first type material. A well of the second-type material within the electrically isolated region of the first type material is formed and a first-type semiconductor device is disposed to receive a second body biasing voltage from the well of second-type material.
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Citations
18 Claims
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1. An integrated circuit including:
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a first plurality of n-type active devices configured to accept a first n-type body biasing voltage; a first plurality of p-type active devices configured to accept a first p-type body biasing voltage; a second plurality of n-type active devices configured to accept a second n-type body biasing voltage; a second plurality of p-type active devices configured to accept a second p-type body biasing voltage; wherein the body terminals of the first plurality of n-type active devices and the body terminals of the first plurality of p-type active devices and the body terminals of the second plurality of n-type active devices and the body terminals of the second plurality of p-type active devices are configured to be electrically isolated from one another; wherein the first plurality of n-type active devices and the first plurality of p-type active devices are operable to operate at an increased frequency in response to the first plurality of n-type active devices and the first plurality of p-type active devices receiving body bias compared to an unbiased condition; and wherein the second plurality of n-type active devices and the second plurality of p-type active devices are operable to operate at a decreased upper frequency limit in response to the second plurality of n-type active devices and the second plurality of p-type active devices receiving body bias compared to an unbiased condition. - View Dependent Claims (2, 3, 4, 5, 18)
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6. An integrated circuit comprising:
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means for applying a first pair of body biasing voltages to circuitry of a first body biasing domain; means for applying a second pair of body biasing voltages to circuitry of a second body biasing domain; and means for performing a function characteristic of the integrated circuit, the function utilizing the circuitry of the second body biasing domain as biased by the second pair of body biasing voltages, the means for performing a function configured to be responsive to the means for applying the second pair of body biasing voltages wherein the means for applying the first pair of body biasing voltages includes a configuration to increase a frequency of operation for the circuitry means of the first body biasing domain compared to nominal and wherein the means for applying the second pair of body biasing voltages includes a configuration to decrease an upper frequency of operation for the circuitry means of the second body biasing domain compared to nominal. - View Dependent Claims (7, 8, 9, 10)
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11. An integrated circuit comprising:
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a first body biasing domain comprising a first plurality of nFET and pFET devices; a second body biasing domain comprising a second plurality of nFET and pFET devices; wherein said first plurality of nFET and pFET devices are configured to receive a first nFET and a first pFET body biasing voltages; wherein said second plurality of nFET and pFET devices are configured to receive a second nFET and a second pFET body biasing voltages; and wherein said integrated circuit is configured to apply said first nFET and said first pFET body biasing voltages independent of other body biasing voltages within said integrated circuit, wherein said first body biasing domain is operable to operate at an increased frequency responsive to said first nFET and said first pFET body biasing voltages and said second body biasing domain is operable to operate at a decreased upper frequency limit responsive to said second nFET and second first pFET body biasing voltages. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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Specification