Integrated circuit including isolation regions substantially through substrate

• US 7,816,759 B2
• Filed: 01/09/2008
• Issued: 10/19/2010
• Est. Priority Date: 01/09/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Tilke, Armin
• Primary Examiner(s): Blum; David S
• Application Number:
  US11/971,374
• Publication Number:
  US 20090174027A1
• Time in Patent Office: 1,014 Days
• Field of Search: 257/506, 257/532, 257/513, 257/E21.546, 257/E21.008, 257/E23.002
• US Class Current: 257/506
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 23/58 Structural electrical arrangements for semiconductor devices not otherwise provided for , e.g. in combination with batteries H01L23/49593, H01L23/49596 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated circuit including a substrate and trench isolation regions. The substrate supports a device. The trench isolation regions are configured to laterally isolate the device. The trench isolation regions extend substantially through the substrate.

Claims

1. An integrated circuit comprising:

a substrate that supports a device; and

a trench isolation region configured to laterally isolate the device, wherein the trench isolation region extends substantially through the substrate and comprises;

a liner region in contact with the substrate and lining a sidewall surface of the trench isolation region, wherein the liner region extends substantially through the substrate and has a higher doping concentration than the substrate.

2. The integrated circuit of claim 1, comprising:

a polished backside including the substrate and the trench isolation region.

3. The integrated circuit of claim 1, comprising:

a backside; and

an insulator situated on the backside, wherein the insulator is situated on the substrate and the trench isolation region.

4. The integrated circuit of claim 3, wherein the insulator is a nitride dielectric.

5. The integrated circuit of claim 1, comprising:

an epitaxial layer over the substrate, wherein the trench isolation region extends substantially from the epitaxial layer through the substrate.

6. The integrated circuit of claim 1, comprising:

an epitaxial layer in contact with the substrate, wherein the substrate is one of an n-plus substrate and a p-plus substrate.

7. The integrated circuit of claim 1, comprising:

an epitaxial layer; and

a buried layer between the substrate and the epitaxial layer.

8. The integrated circuit of claim 1, wherein the integrated circuit is part of a semiconductor wafer.

9. An integrated circuit comprising:

a backside dielectric layer;

an n-minus substrate layer on the backside dielectric layer;

an n-plus buried layer on the n-minus substrate layer and separated from the backside dielectric layer via the n-minus substrate layer;

an epitaxial layer on the n-plus buried layer and separated from the n-minus substrate layer via the n-plus buried layer; and

a deep trench isolation region configured to laterally isolate at least one device in the epitaxial layer and extending to the backside dielectric layer.

10. The integrated circuit of claim 9, comprising:

a sinker configured to extend through the epitaxial layer and contact the n-plus buried layer.

11. The integrated circuit of claim 9, wherein the deep trench isolation region comprises:

an n-doped dielectric liner.

12. The integrated circuit of claim 11, wherein the deep trench isolation region comprises a liner region lining a sidewall surface of the deep trench isolation region and extending substantially through the n-minus substrate layer, the n-plus buried layer, and the epitaxial layer, wherein the liner region includes electrons from the n-doped dielectric liner.

13. The integrated circuit of claim 9, wherein the deep trench isolation region comprises one of:

an n-plus polysilicon liner, carbon, and silicide.

14. The integrated circuit of claim 13, wherein the deep trench isolation region comprises a liner region lining a sidewall surface of the deep trench isolation region and extending substantially through the n-minus substrate layer, the n-plus buried layer, and the epitaxial layer, wherein the liner region includes electrons from the n-plus polysilicon liner.

16. The integrated circuit of claim 9, comprising:

a polished backside including the n-minus substrate layer and the deep trench isolation region.

15. An integrated circuit comprising:

a substrate that supports a device; and

a deep trench isolation region extending through the substrate and comprising an n-plus liner in contact with the substrate, wherein the n-plus liner lines a sidewall surface of the deep trench isolation region and extends through the substrate.

17. An integrated circuit comprising:

an n-minus substrate;

an n-plus buried layer on the n-minus substrate;

an epitaxial layer on the n-plus buried layer; and

a deep trench isolation region configured to laterally isolate at least one device in the epitaxial layer, wherein the deep trench isolation region comprises;

a liner region lining a sidewall surface of the deep trench isolation region and extending substantially through the n-minus substrate layer, the n-plus buried layer, and the epitaxial layer, wherein the liner region includes electrons from an n-doped dielectric liner and has higher n-type doping concentrations than portions of the n-minus substrate layer, the n-plus buried layer, and the epitaxial layer adjacent the liner region.

18. The integrated circuit of claim 17, wherein the deep trench isolation region includes the n-doped dielectric liner.