Power line control system

• US 7,816,803 B1
• Filed: 08/30/2007
• Issued: 10/19/2010
• Est. Priority Date: 08/30/2007
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Wang, Jingming, Luo, Jianding, Notohamiprodjo, Hubertus
• Primary Examiner(s): Deberadinis; Robert L.
• Application Number:
  US11/848,078
• Time in Patent Office: 1,146 Days
• Field of Search: 307/149, 307/3
• US Class Current: 307/3
• CPC Class Codes: H04B 2203/5408 using protocols
• CPC Class Codes: H04B 3/542 the information being in digital form
• CPC Class Codes: H04L 7/04 Speed or phase control by synchronisation signals H04L7/0075 takes precedence

Abstract

A system and method for processing data includes coupling circuitry for connecting a system to a power line and receiving data from the power line, packet detection circuitry for detecting synch mark in the data, and a processor for processing data upon detecting a synch mark.

Claims

1. An apparatus for processing data over a power line, said apparatus comprising:

coupling circuitry for connecting said apparatus to the power line;

packet detection circuitry for detecting a synch mark in said data, said data containing blocks of the synch mark interspersed with blocks of payload, and the synch mark indicating that there are data packets to be processed; and

a processor configured to process said payload upon said packet detection circuitry detecting said synch mark.

2. The apparatus of claim 1, wherein the synch mark comprises a fixed number of bits and a first block of the synch mark comprises a greater number of the bits than do subsequent blocks of the synch mark.

3. The apparatus of claim 1, wherein the data comprises an error correcting code, and wherein the packet detection circuitry is configured to process the error correcting code.

4. The apparatus of claim 1, further comprising:

circuitry capable of instructing the processor to process data upon detecting the synch mark.

5. The apparatus of claim 1, wherein the processor is configured to produce data packets with an interspersed synch mark to be transmitted over the power line.

6. The apparatus of claim 1, wherein the packet detection circuitry is capable of detecting synch marks being transmitted at more than one frequency.

7. The apparatus of claim 1, wherein the packet detection circuitry samples said data at a rate at least twice a transmission rate of said data.

8. The apparatus of claim 1, wherein the synch mark corresponds to a network address of a device coupled to the power line.

9. The apparatus of claim 1, wherein the synch mark is common to all devices coupled to the power line.

10. A method for processing data over a power line, said method comprising:

responsive to receiving data from said power line, detecting a synch mark in said data, said data containing blocks of said synch mark interspersed with blocks of payload and the synch mark indicating that there are data packets to be processed;

upon detection of said synch mark, instructing a processor to process said payload.

11. The method of claim 10, wherein said synch mark comprises a fixed number of bits and a first block of said synch mark comprises a greater number of said bits than do subsequent blocks of said synch mark.

12. The method of claim 10, further comprising:

processing an error correcting code, said data comprising said error correcting code.

13. The method of claim 10, further comprising:

producing data packets with an interspersed synch mark to be transmitted over said power line.

14. The method of claim 10, further comprising:

detecting synch marks being transmitted at more than one frequency.

15. The method of claim 10, further comprising:

sampling said data at a rate at least twice a transmission rate of said data.

16. An apparatus for processing data over a power line, said apparatus comprising:

coupling means for coupling said apparatus to said power line;

detection means for detecting a synch mark in said data, said data containing blocks of said synch mark interspersed with blocks of payload, and the synch mark indicating that there are data packets to be processed;

processing means for processing said payload upon said detection means detecting said said synch mark.

17. The apparatus of claim 16, wherein said synch mark comprises a fixed number of bits and a first block of said synch mark comprises a greater number of said bits than do subsequent blocks of said synch mark.

18. The apparatus of claim 16, wherein said data comprises an error correcting code, and wherein said detection means is configured to process said error correcting code.

19. The apparatus of claim 16, further comprising:

circuit means capable of instructing the processing means to process data upon detecting said synch mark.

20. The apparatus of claim 16, wherein said processing means is configured to produce data packets with an interspersed synch mark to be transmitted over said power line.

21. The apparatus of claim 16, wherein said detection means is capable of detecting synch marks being transmitted at more than one frequency.

22. The apparatus of claim 16, wherein said detection means samples said data at a rate at least twice a transmission rate of said data.