Variable width writing to a memory of an IC

• US 7,816,944 B2
• Filed: 10/28/2007
• Issued: 10/19/2010
• Est. Priority Date: 03/15/2005
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Hutchings, Brad
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US11/926,100
• Publication Number:
  US 20080100336A1
• Time in Patent Office: 1,087 Days
• Field of Search: 326 38- 41, 326/113
• US Class Current: 326/38
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

Some embodiments of the invention provide a configurable integrated circuit (“IC”). This IC includes several configurable circuits for receiving configuration data and configurably performing a set of operations based on the configuration data. It also includes several hybrid circuits. Each particular hybrid circuit can interchangeably perform as either a logic circuit or an interconnect circuit in the configurable IC.

Claims

1. An integrated circuit (IC) comprising:

a) a plurality of configurable logic circuits for configurably performing different logic operations;

b) a plurality of interconnect circuits;

c) a plurality of memories for inputting, storing, and outputting data; and

d) a set of multiplexers, each multiplexer comprising a select terminal set and an input terminal set,

wherein each particular multiplexer is for (i) receiving at the input terminal set, a set of data and (ii) selectively outputting, to a particular memory, a subset of the received set of data based on a signal received at the select terminal set, wherein the select terminal set is coupled to a particular interconnect circuit that controllably connects the select terminal set to a configuration data storage element and an output of a particular configurable logic circuit.

2. The IC of claim 1, wherein each particular memory is for storing non-configuration data.

3. The IC of claim 1, wherein the plurality of interconnect circuits is a plurality of configurable interconnect circuits, each for configurably routing signals between configurable logic circuits.

4. The IC of claim 3, wherein the set of data comprises a first set of data from the particular memory and a second set of data not from the particular memory, wherein at least one of the particular multiplexers receives the second set of data through a particular set of configurable interconnect circuits.

5. The IC of claim 3, wherein for at least one of the particular multiplexers, the set of data comprises a first set of data from the particular memory and a second set of data not from the particular memory, wherein the particular multiplexer receives the first set of data through a particular set of configurable interconnect circuits.

6. The IC of claim 3, wherein said outputting to the particular memory is through a particular set of configurable interconnect circuits.

7. The IC of claim 5, wherein the second set of data is output by at least one configurable logic circuit.

8. The IC of claim 5, wherein said first set of data is received from a location in the particular memory, wherein said outputting to the particular memory comprises overwriting said location in the particular memory.

9. The IC of claim 8, wherein the particular memory is a non-configurable memory for receiving only a fixed amount of data in parallel for each write to the memory.

10. The IC of claim 8, wherein the particular memory is a non-configurable memory for outputting only a fixed amount of data in parallel for each read from the memory.

11. A method of selectively outputting data in an integrated circuit (IC) comprising a memory, a plurality of configurable logic circuits, and a plurality of multiplexers, each multiplexer comprising an input terminal set and a select terminal set, the method comprising:

at a particular multiplexer;

a) receiving at the input terminal set, a set of input values comprising non-configuration user-design data generated by configurable logic circuits;

b) receiving at the select terminal set, a user signal generated within the IC; and

c) based on the received user signal, outputting to the memory a subset of the set of input values, wherein the subset has fewer values than the set of input values.

12. The method of claim 11, wherein the plurality of configurable logic circuits is for configurably performing logic operations, wherein the user signal comprises an output of at least one configurable logic circuit.

13. The method of claim 11, wherein the subset of the set of input values is provided by the memory.

14. An integrated circuit (IC) comprising:

a) a contiguous memory block for receiving and storing multi-bit data in parallel;

b) a plurality of configurable logic circuits for configurably performing different logic operations; and

c) a plurality of multiplexers, each multiplexer for (i) receiving a set of input values and (ii) based on a select signal comprising an output of a particular configurable logic circuit, outputting a subset of the received set of input values to write to the contiguous memory block, wherein a set of outputs of the plurality of multiplexers is a multi-bit subset of the received sets of input values with fewer input values than the received sets of input values.

15. The IC of claim 14, wherein the subset of the received sets of input values that is output from the plurality of multiplexers is stored by the contiguous memory block.

16. The IC of claim 14, wherein each multiplexer comprises a plurality of two to one multiplexers that each receive a common select signal.

17. A method for writing data in parallel to a contiguous memory block that stores multi-bit data in an integrated circuit (IC) comprising a plurality of configurable logic circuits for configurably performing logic operations and a plurality of multiplexers, the method comprising:

at a particular multiplexer;

a) receiving a set of input values;

b) receiving a set of select signals comprising an output of at least one configurable logic circuit; and

c) based on the received set of select signals, outputting to the contiguous memory block a multi-bit subset of the set of input values with fewer values than the received set of input values, wherein said multi-bit subset is output to the contiguous memory block in parallel.

18. The method of claim 17, wherein a subset of the received set of input values is supplied by the contiguous memory block.

19. A method of performing a read and write-back operation in an integrated circuit (IC), the IC comprising (i) a memory, (ii) a plurality of configurable logic circuits for configurably performing different logic operations, and (iii) a set of multiplexers, each multiplexer comprising an input terminal set and a select terminal set, the method comprising:

a) at the memory, receiving a location of a stored first set of data;

b) reading the first set of data from the memory;

c) supplying the first set of data to the set of multiplexers;

d) at the set of multiplexers, receiving a second set of data; and

e) from the set of multiplexers, supplying a subset of the first set of data and a subset of the second set of data to the memory, in order to change at least a portion of the stored first set of data at the location.

20. The method of claim 19, wherein at least one multiplexer comprises a plurality of two to one multiplexers that each receives a common select signal.

21. The method of claim 19, wherein the IC further comprises a plurality of configurable interconnect circuits for configurably routing signals between the plurality of configurable logic circuits, wherein the first set of data is supplied to the set of multiplexers through a set of configurable interconnect circuits.

22. The method of claim 19, wherein the IC further comprises a plurality of configurable interconnect circuits for configurably routing signals between the plurality of configurable logic circuits, wherein the memory receives the subset of the first set of data and the subset of the second set of data through a set of configurable interconnect circuits.

23. The method of claim 19, wherein the second set of data is provided by at least one configurable logic circuit.

24. The method of claim 19, wherein the memory is for storing non-configuration user-design data.

25. The method of claim 19, wherein the memory comprises a contiguous memory block.