Non-volatile memory serial core architecture

• US 7,817,470 B2
• Filed: 11/23/2007
• Issued: 10/19/2010
• Est. Priority Date: 11/27/2006
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Kim, Jin-Ki
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US11/944,535
• Publication Number:
  US 20080123423A1
• Time in Patent Office: 1,061 Days
• Field of Search: 365/185.11 O, 365/185.18, 365/185.33, 365/219.X, 365/220, 365/221, 365/185.11, 365/219
• US Class Current: 365/185.11
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
• CPC Class Codes: G11C 2216/20 Suspension of programming or erasing cells in an array in order to read other cells in it
• CPC Class Codes: G11C 2216/30 Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1033 using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1042 : using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: G11C 7/1048 : Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/12 : Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. The memory bank is divided into two halves, where each half is divided into upper and lower sectors. Each sector provides data in parallel to a shared two-dimensional page buffer with an integrated self column decoding circuit. A serial to parallel data converter within the memory bank couples the parallel data from either half to the serial data path core. The shared two-dimensional page buffer with the integrated self column decoding circuit minimizes circuit and chip area overhead for each bank, and the serial data path core reduces chip area typically used for routing wide data buses. Therefore a multiple memory bank system is implemented without a significant corresponding chip area increase when compared to a single memory bank system having the same density.

Claims

1. A memory system comprising:

a memory bank having

a first bank half coupled to first n parallel datalines where n is an integer value greater than 0, the first bank half including

a first sector having wordlines and bitlines coupled to memory cells,

a second sector having wordlines and bitlines coupled to memory cells, and

a page buffer selectively coupled to bitlines of one of the first sector and the second sector, the page buffer being coupled to the first n parallel datalines

a second bank half coupled to second n parallel datalines, and

a data converter

for selectively converting one of the first and the second n parallel datalines into serial bitstream read data and

for selectively converting serial bitstream write data into parallel data for one of the first and the second n parallel datalines, the memory bank

providing the serial bitstream read data in response to a read operation and

for receiving the serial bitstream write data in response to a write operation

and,

a serial data path for coupling the serial bitstream read data and the serial bitstream write data between the memory bank and input/output ports.

2. The memory system of claim 1, wherein the serial data path includes

a data arbitrator for receiving access data serially from the input/output ports, the access data including a command and an address,

the data arbitrator being configured

to convert the command and the address into a parallel format, and

to pass the serial bitstream read data to the input/output ports during the read operation.

3. The memory system of claim 1, wherein the page buffer is a first page buffer, and second bank half includes

a third sector having wordlines and bitlines coupled to memory cells,

a fourth sector having wordlines and bitlines coupled to memory cells, and,

a second page buffer selectively coupled to bitlines of one of the third sector and the fourth sector, the second page buffer being coupled to the second n parallel datalines.

4. The memory system of claim 3, wherein the bitlines of the first sector and the second sector are grouped into sets of bitlines, each of the sets of bitlines being coupled to a common bitline, the common bitline being coupled to the first page buffer.

5. The memory system of claim 3, wherein the bitlines of the third sector and the fourth sector are grouped into sets of bitlines, each of the sets of bitlines being coupled to a common bitline, the common bitline being coupled to the second page buffer.

6. The memory system of claim 1, wherein the data converter includes

a first converter for sequentially coupling each of the first n parallel datalines to a first terminal,

a second converter for sequentially coupling each of the second n parallel datalines to a second terminal,

a data path selector for selectively coupling one of the first terminal and the second terminal to a bidirectional serial data line.

7. The memory system of claim 6, further including

control logic for receiving a command and an address for operating the memory bank, the data converter and the serial data path during the read operation.

8. The memory system of claim 1, further including another memory bank for providing the serial bitstream read data in response to the read operation and for receiving the serial bitstream write data in response to the write operation.

9. The memory system of claim 8, wherein the serial data path includes a data switcher

for selectively coupling the serial bitstream write data to one of the memory bank and the another memory bank, and

for selectively coupling the serial bitstream read data from one of the memory bank and the another memory bank to the data arbitrator of the serial data path.

10. The memory system of claim 8, further including another serial data path

for coupling the serial bitstream read data from one of the memory bank and the another memory bank to other input/output ports, and

for coupling the serial bitstream write data to one of the memory bank and the another memory bank.

11. The memory system of claim 10, wherein the another serial data path includes

a second data switcher

for selectively coupling the serial bitstream write data to one of the another memory bank and the data switcher, and

for selectively coupling the serial bitstream read data to one of the data switcher and another data arbitrator.

12. The memory system of claim 11, further including a serial transfer dataline for coupling the data switcher to the second data switcher.

13. The memory system of claim 8, further comprising a serial transfer switch for selectively coupling the serial bitstream read data from one of the memory bank and the another memory bank to the serial data path.

27. The memory system of claim 1, wherein the input/output ports are included in an input/output interface.

14. A memory system comprising:

a memory bank for providing serial bitstream read data in response to a read operation and for receiving serial bitstream write data in response to a write operation, the memory bank having

a first bank half coupled to first n parallel datalines where n is an integer value greater than 0,

a second bank half coupled to second n parallel datalines,

a first data converter for sequentially coupling each of the first n parallel datalines to a first terminal

in the read operation to convert parallel read data into the serial bitstream read data, and

in the write operation to convert the serial bitstream write data into parallel write data,

a second data converter for sequentially coupling each of the second n parallel datalines to a second terminal

in the read operation to convert parallel read data into the serial bitstream read data, and

in the write operation to convert the serial bitstream write data into parallel write data,

a data path selector for selectively coupling one of the first terminal and the second terminal to a bidirectional serial data line,

and,

a serial data path for coupling either one of the serial bitstream read data and the serial bitstream write data on the bidirectional serial data line to input/output ports.

15. The memory system of claim 14, wherein the serial data path includes

a data arbitrator for receiving access data serially from the input/output ports, the access data including a command and an address,

the data arbitrator being configured

to convert the command and the address into a parallel format, and

to pass the serial bitstream read data to the input/output ports during the read operation.

16. The memory system of claim 14, wherein the first bank half includes

a first sector having wordlines and bitlines coupled to memory cells,

a second sector having wordlines and bitlines coupled to memory cells, and,

a first page buffer selectively coupled to bitlines of one of the first sector and the second sector, the first page buffer being coupled to the first n parallel datalines.

17. The memory system of claim 16, wherein the second bank half includes

a third sector having wordlines and bitlines coupled to memory cells,

a fourth sector having wordlines and bitlines coupled to memory cells, and,

a second page buffer selectively coupled to bitlines of one of the third sector and the fourth sector, the second page buffer being coupled to the second n parallel datalines.

18. The memory system of claim 17, wherein the bitlines of the first sector and the second sector are grouped into sets of bitlines, each of the sets of bitlines being coupled to a common bitline, the common bitline being coupled to the first page buffer.

19. The memory system of claim 17, wherein the bitlines of the third sector and the fourth sector are grouped into sets of bitlines, each of the sets of bitlines being coupled to a common bitline, the common bitline being coupled to the second page buffer.

20. The memory system of claim 14, further including

control logic for receiving a command and an address for operating the memory bank, the first data converter, the second data converter and the serial data path during the read operation.

21. The memory system of claim 14, further including another memory bank for providing the serial bitstream read data in response to the read operation and for receiving the serial bitstream write data in response to the write operation.

22. The memory system of claim 21, wherein the serial data path includes a data switcher

for selectively coupling the serial bitstream write data to one of the memory bank and the another memory bank, and

for selectively coupling the serial bitstream read data from one of the memory bank and the another memory bank to the data arbitrator of the serial data path.

23. The memory system of claim 21, further including another serial data path

for coupling the serial bitstream read data from one of the memory bank and the another memory bank to other input/output ports, and

for coupling the serial bitstream write data to one of the memory bank and the another memory bank.

24. The memory system of claim 23, wherein the another serial data path includes

a second data switcher for selectively coupling the serial bitstream write data to one of the another memory bank and the data switcher, and for selectively coupling the serial bitstream read data to one of the data switcher and another data arbitrator.

25. The memory system of claim 24, further including a serial transfer dataline for coupling the data switcher to the second data switcher.

26. The memory system of claim 21, further comprising a serial transfer switch for selectively coupling the serial bitstream read data from one of the memory bank and the another memory bank to the serial data path.

28. The memory system of claim 14, wherein the input/output ports are included in an input/output interface.