Jitter buffer for a circuit emulation service over an internal protocol network

• US 7,817,545 B2
• Filed: 09/27/2006
• Issued: 10/19/2010
• Est. Priority Date: 08/19/1999
• Status: Expired due to Fees

• Current Assignee: Nokia Technologies Oy (Nokia Corporation)
• Original Assignee: Nokia Corporation
• Inventors: Ho, Chi Fai, Merchant, Shashank, Merani, Lalit, Bhat, Ravi Bail, Kondapalli, Raghu R., Kejriwal, Prabhas
• Primary Examiner(s): Jagannathan; Melanie
• Application Number:
  US11/527,596
• Publication Number:
  US 20070019547A1
• Time in Patent Office: 1,483 Days
• Field of Search: None
• US Class Current: 370/231
• CPC Class Codes: H04L 12/6418 Hybrid transport
• CPC Class Codes: H04L 2012/6472 Internet
• CPC Class Codes: H04L 2012/6475 N-ISDN, Public Switched Telephone Network [PSTN]
• CPC Class Codes: H04L 2012/6481 Speech, voice

Abstract

A jitter buffer receives a plurality of data packets comprising a circuit emulation service over internet protocol (CESIP), buffers the plurality of data packets, and plays data from the plurality of data packets at a constant bit rate corresponding to the CESIP.

Claims

1. An apparatus comprising:

a receiver configured to receive circuit emulation service over internet protocol data packets each comprising data for a plurality of circuits;

a first jitter buffer configured to store a first plurality of data packets for a first circuit of the plurality of circuits, each of said first plurality of data packets comprising at least a portion of a first stream of data of the first circuit, each of said first plurality of data packets comprising a packet header that comprises a packet sequence number representing an offset value for the packet with respect to a reference point of the first stream of data; and

a control unit controller to direct, based on the packet sequence number, individual ones of the first plurality of data packets to a data slot in the first jitter buffer as the first plurality of data packets are received, and to play data from the plurality of data slots at a first constant bit rate corresponding to the first circuit, and wherein the controller is also configured to indicate a first position of the first jitter buffer that indicates a next position from which the data is to be played, and a second position of the first jitter buffer that indicates a packet having a highest packet sequence number;

a second jitter buffer configured to store a second plurality of data packets for a second circuit of the plurality of circuits, each of said second plurality of data packets comprising at least a portion of a second stream of data of the second circuit, each of said second plurality of data packets comprising said packet header that comprises a packet sequence number representing an offset value for the packet with respect to a reference point of the second stream of data;

where said control unit controller is further configured to direct, based on the packet sequence number, individual ones of the second plurality of data packets to a data slot in the second jitter buffer as the second plurality of data packets are received, and to play data from the plurality of data slots at a second constant bit rate corresponding to the second circuit emulation service over internet protocol.

2. The apparatus of claim 1, wherein the first and second jitter buffers comprise a random access memory.

3. The apparatus of claim 1, wherein the controller comprises at least one of a processor unit to run software, an application specific integrated circuit, and a programmable gate array.