Test device and a test method

• US 7,817,654 B2
• Filed: 05/27/2008
• Issued: 10/19/2010
• Est. Priority Date: 05/26/2007
• Status: Active Grant

• Current Assignee: Vector Informatik GmbH
• Original Assignee: Vector Informatik GmbH
• Inventors: Fischer, Markus, Braun, Jochen, Augustin, Olav, Gossner, Martin
• Primary Examiner(s): Kumar; Pankaj
• Assistant Examiner(s): Sweet; Lonnie
• Application Number:
  US12/127,715
• Publication Number:
  US 20090041047A1
• Time in Patent Office: 875 Days
• Field of Search: 370/402, 370/412, 702/122, 709/253
• US Class Current: 370/412
• CPC Class Codes: H04L 12/403 with centralised control, e.g. polling
• CPC Class Codes: H04L 2012/40273 the transportation system being a vehicle
• CPC Class Codes: H04L 43/50 Testing arrangements
• CPC Class Codes: H04L 49/90 Buffering arrangements

Abstract

A test device and a test method, the test device comprising a bus controller for the transmission and reception of bus messages, the bus controller having a message memory for offering transmission data for bus messages, the message memory having a memory capacity for a bus message sequence with bus messages to be transmitted within a single transmission cycle or a transmission cycle sequence. The test device includes an intermediate memory for the storage of transmission data for bus messages with a larger storage capacity than the message memory. The test device furthermore comprises a transmission preparing means for reading transmission data from the intermediate memory and for writing, in advance of reading of the bus controller, to the message memory of the bus controller so that the bus message sequence is expanded by additional bus messages which are transmitted by the bus controller within the transmission cycle or the transmission cycle sequence on the motor vehicle bus.

Claims

1. A test device for a motor vehicle bus, the test device comprising:

a bus controller for the transmission and reception of bus messages, the bus controller having a message memory for offering transmission data for bus messages, the message memory having a storage capacity for one bus message sequence with bus messages to be transmitted within a single transmission cycle or a transmission cycle sequence;

an intermediate memory for the storage of transmission data for bus messages with a larger storage capacity than the message memory; and

a transmission preparing means for reading the transmission data from the intermediate memory and for writing, preceding a reading of the bus controller, to the message memory of the bus controller so that the bus message sequence is expanded by additional bus messages, which are transmitted by the bus controller within the transmission cycle or the transmission cycle sequence on the motor vehicle bus

wherein the transmission preparing means comprises a head preparing means for writing head data to the message memory and a user data preparing means for writing user data to the message memory, the head data being provided for the production of message heads of the bus message and the user data being provided for the user data respectively following the message heads, of the bus messages, the head preparing means writing the message heads, before the user data preparing means writes the associated user data to the message memory, so that the user data preparing means can modify the user data during an locked phase, in which the bus controller in advance blocks the writing of message heads to the message memory prior to the transmission of a respective bus message.

2. The test device as set forth in claim 1, wherein the storage capacity of the message memory is provided for a maximum number of bus messages dependent on a size of the bus messages.

3. The test device as set forth in claim 1, wherein the bus is designed for time division multiple access, and is more particularly a FlexRay bus.

4. The test device as set forth in claim 1, wherein for the reception of transmission data to be written to the intermediate memory the test device comprises a control interface for an operating means and more particularly a personal computer.

5. The test device as set forth in claim 1, wherein the test device comprises means for the transmission of acknowledging messages by way of a control interface, the acknowledging messages acknowledging bus messages that are transmitted on the motor vehicle bus by the bus controller.

6. The test device as set forth in claim 4, wherein the test device comprises means for reading out received bus messages from the message memory and for the transfer of the received bus messages to the intermediate memory and/or the control interface, the test device reading a memory location containing a received bus message of the message memory before rewriting by the bus controller.

7. The test device as set forth in claim 5, wherein the acknowledging messages contain the content of the transmitted bus messages completely or partially.

8. The test device as set forth in claim 1, wherein the bus controller comprises means for writing bus messages of other bus subscribers to the message memory which are transmitted by other bus subscribers between bus messages respectively to be transmitted by other bus subscribers within or outside the bus message sequence.

9. The test device as set forth in claim 1 further comprising a receiving means which gives the bus controller control instructions for the reception of bus messages at predetermined transmission slots of the motor vehicle bus.

10. The test device as set forth in claim 9, wherein the receiving means comprises means for writing a received mark for transmission slots to the bus controller at which the bus controller is to receive bus messages.

11. The test device as set forth in claim 10, wherein each memory location of the message memory is associated with the transmission location of the motor vehicle bus and that the receiving means comprises means for marking memory locations for respective bus messages to be received in the message memory with the received mark, the bus controller writing the received bus messages to the memory locations provided with the mark.

12. The test device as set forth in claim 10, wherein the bus controller writes a zero mark or a zero information mark to memory locations, if the memory location has a received mark associated with it and the bus controller has not received any bus message or a bus message with zero information to the respective transmission slot and that the receiving means comprises means for the issue of the zero mark and the zero information mark to the control interface.

13. The test device as set forth in claim 1, wherein the bus messages received in the message memory and to be transmitted are be stored.