Method and apparatus for aggregating input data streams

• US 7,817,659 B2
• Filed: 03/26/2004
• Issued: 10/19/2010
• Est. Priority Date: 03/26/2004
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Foundry Networks LLC (Broadcom, Inc.)
• Inventors: Wong, Yuen Fai, Lin, Yu-Mei, Grenier, Richard A.
• Primary Examiner(s): Ngo; Ricky
• Assistant Examiner(s): PATEL, CHANDRAHAS B
• Application Number:
  US10/810,208
• Publication Number:
  US 20090279559A1
• Time in Patent Office: 2,398 Days
• Field of Search: 370/389, 370/473, 370/428, 370/400, 370/474, 370/535, 370/536, 370/537, 370/538, 370/539, 370/540, 370/541, 370/542, 370/543, 370/544, 370/545
• US Class Current: 370/428
• CPC Class Codes: H04L 47/2433 Allocation of priorities to traffic types
• CPC Class Codes: H04L 47/6275 based on priority
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/352 Gigabit ethernet switching [GBPS]

Abstract

A method and apparatus aggregate a plurality of input data streams from first processors into one data stream for a second processor, the circuit and the first and second processors being provided on an electronic circuit substrate. The aggregation circuit includes (a) a plurality of ingress data ports, each ingress data port adapted to receive an input data stream from a corresponding first processor, each input data stream formed of ingress data packets, each ingress data packet including priority factors coded therein, (b) an aggregation module coupled to the ingress data ports, adapted to analyze and combine the plurality of input data steams into one aggregated data stream in response to the priority factors, (c) a memory coupled to the aggregation module, adapted to store analyzed data packets, and (d) an output data port coupled to the aggregation module, adapted to output the aggregated data stream to the second processor.

Claims

1. A circuit for aggregating a plurality of input data streams from first processors into one data stream for a second processor, said circuit comprising:

a plurality of ingress data ports, each said ingress data port coupled to a corresponding first processor and adapted to receive an input data stream from the corresponding first processor, each input data stream comprising ingress data packets, each ingress data packet comprising at least one priority factor coded therein;

an aggregation module coupled to said plurality of ingress data ports and configured to receive the plurality of input data streams from the first processors using the plurality of ingress data ports, wherein an input data stream from a first processor is received via the ingress data port coupled to the first processor, said aggregation module adapted to analyze and combine the plurality of input data streams into one aggregated data stream in response to the at least one priority factor and to generate a packet descriptor comprising a reference to a memory location of its analyzed data packet;

a memory coupled to said aggregation module, said memory adapted to store analyzed data packets;

said memory comprising a plurality of priority queues each provided for a corresponding priority class, adapted to store the packet descriptor of each of the analyzed data packets classified to the corresponding priority class, the packet descriptor containing a reference to the memory location of its analyzed data packet in said memory; and

an output data port coupled to said aggregation module, said output data port adapted to output the aggregated data stream to the second processor.

2. The circuit of claim 1, wherein each of the first processors and the second processor transmits and receives a data stream through a logical interface providing logical interconnection between a Media Access Control sublayer (MAC) and a Physical layer (PHY).

3. The circuit of claim 1, wherein the first processors are Layer-2 switching processors.

4. The circuit of claim 1, wherein the second processor is a data packet processor.

5. The circuit of claim 1, wherein said memory is an external buffer memory.

6. The circuit of claim 1, further comprising:

an egress data input port adapted to receive a data stream from the second processor, the data stream comprising egress data packets;

a plurality of egress data output ports, each adapted to output an output data stream to a corresponding one of the first processors; and

a forwarding module coupled between said egress data input port and said egress data output port, said forwarding module adapted to forward an egress data packet in the data stream from the second processor to one of the egress data output port in response to destination information associated with said egress data packet.

7. The circuit of claim 1, wherein:

said ingress data ports comprise a first data port for receiving a first input data stream and a second data port for receiving a second input data stream; and

said aggregation module comprises;

a first packet analyzer coupled to said first data port, adapted to classify each of the ingress data packets in the first data stream into one of predetermined priority classes based on the at least one priority factor;

a second packet analyzer coupled to said second data port, adapted to classify each of the ingress data packets in the second data stream into one of predetermined priority classes based on the at least one priority factor;

a queue module having

a selection logic implementing a queue scheme, adapted to arbitrate and select a packet descriptor from among the priority queues;

a first write interface coupled to said first packet analyzer, adapted to write the analyzed data packets into said memory at the memory location indicated by the corresponding packet descriptor;

a second write interface coupled to said second packet analyzer, adapted to write the analyzed data packets into said memory at the memory location indicated by the corresponding packet descriptor;

a common read interface coupled to said queue selection logic, adapted to read a data packet corresponding to the selected packet descriptor from said memory; and

an output module to send the data packets read from said memory to said output data port as the aggregated data stream.

8. The circuit of claim 7, wherein:

said first packet analyzer comprises a first data decoder coupled to said first ingress data port, adapted to decode a header of each ingress data packet to extract the at least one priority factor; and

said second packet analyzer comprises a second data decoder coupled to said second ingress data port, adapted to decode a header of each ingress data packet to extract the at least one priority factor.

9. The circuit of claim 7, wherein said output module comprises:

a read buffer coupled to said common read interface.

10. The circuit of claim 9, wherein said output module further comprising:

a data encoder coupled to said read buffer, adapted to encode the data packets into an interface format corresponding to the first interfaces before sending from the output data port.

11. The circuit of claim 7, wherein said aggregation module further comprises:

a first write buffer coupled between said first packet analyzer and said first write interface; and

a second write buffer coupled between said second packet analyzer and said second write interface.

12. The circuit of claim 11, wherein said aggregation module further comprises:

a flow control module adapted to assert a flow control signal if an amount of data stored in said first or second write buffer exceeds a threshold.

13. The circuit of claim 7, further comprising:

a flow control module adapted to assert a flow control signal if an amount of data stored in a corresponding priority queue in said queue module exceeds a threshold.

14. The circuit of claim 7, further comprising:

an egress data input port adapted to receive a data stream from the second processor, the data stream comprising egress data packets;

a plurality of egress data output ports, each adapted to output an output data stream to a corresponding one of the first processors;

a forwarding module coupled between said egress data input port and said egress data output ports, said forwarding module adapted to forward an egress data packet in the data stream from the second processor to one of the egress data output port in response to destination information associated with each egress data packet.

15. The circuit of claim 14, wherein said aggregation module further comprises:

a flow control module adapted to assert a flow control signal if an amount of data stored in said first or second write buffer exceeds a threshold, or if an amount of data stored in a corresponding priority queue in said queue module exceeds a threshold.

16. The circuit of claim 15, wherein said flow control module sends the flow control signal to said second processor, said second processor insert a pause control packet for said first processors in the data stream.

17. The circuit of claim 1:

wherein the aggregation module is implemented by a programmable device.

18. The circuit of claim 1:

wherein the at least one priority factor comprises an indication of whether the ingress packet contains protocol data or not.

19. The circuit of claim 18, wherein the at least one priority factor further comprises:

per-port priority; and

virtual LAN priority.

20. A circuit for aggregating an input data stream from a first processor into an aggregated data stream for a second processor, said circuit comprising:

a first data link adapted to receive the input data stream from the first processor, the first data link having a first bandwidth, the input data stream comprising ingress data packets, each ingress data packet comprising at least one priority factor coded therein;

an aggregation module coupled to the first data link and adapted to receive the input data stream from the first processor via the first data link, said aggregation module adapted to analyze and selectively recombine the ingress data packets in response to the at least one priority factor so as to generate an aggregated data;

a memory coupled to said aggregation module, said memory adapted to store analyzed data packets; and

a second data link coupled to said aggregation module, the second data link having a second bandwidth smaller than the first bandwidth, said second data link adapted to output the aggregated data stream from the aggregation module to the second processor;

wherein said aggregation module comprises;

a packet analyzer adapted to classify each of the ingress data packets into one of predetermined priority classes based on the at least one priority factor;

a queue module comprising

a plurality of priority queues each provided for the corresponding priority class, adapted to store a packet descriptor of each of the analyzed data packets classified to the corresponding priority class, the packet descriptor containing a reference to a memory location of its analyzed data packet in said memory, and

a selection logic implementing a queue scheme, adapted to arbitrate and select a packet descriptor from among the priority queues;

a read interface coupled to said queue module, adapted to read a data packet corresponding to the selected packet descriptor from said memory; and

an output module to send the data packets read from said memory to the second data link as the aggregated data stream.

21. The circuit of claim 20, wherein the first processor and the second processor comprise an interface providing logical interconnection between a Media Access Control sublayer (MAC) and a Physical layer (PHY).

22. The circuit of claim 20, wherein said memory is an external buffer memory.

23. The circuit of claim 20, further comprising:

a flow control module adapted to assert a flow control signal if an amount of data stored in a corresponding priority queue in said queue module exceeds a threshold.

24. The circuit of claim 20, wherein said packet analyzer comprises:

a data decoder coupled to the first data link, adapted to decode a header of each ingress data packet to extract the at least one priority factor.

25. The circuit of claim 20, wherein said output module comprises:

a read buffer coupled to said read interface.

26. The circuit of claim 25, wherein said output module further comprises:

a data encoder coupled to said read buffer, adapted to encode the data packets before sending using the second data link.

27. The circuit of claim 20, wherein said aggregation module further comprises:

a write interface coupled to said packet analyzer, adapted to write the analyzed data packets into said memory at the memory location indicated by the corresponding packet descriptor.

28. The circuit of claim 27, further comprising:

a write buffer coupled between said packet analyzer and said write interface.

29. The circuit of claim 28, further comprising:

a flow control module adapted to assert a flow control signal if an amount of data stored in said write buffer exceeds a threshold.

30. A method for aggregating a plurality of input data streams from first processors into one data stream for a second processor, said method comprising:

receiving an input data stream from each of the first processors, each input data stream comprising ingress data packets, each ingress data packet comprising at least one priority factor coded therein;

analyzing and classifying each of the ingress data packets into one of predetermined priority classes based on the at least one priority factor;

storing an analyzed data packet in a memory;

generating a packet descriptor for the analyzed ingress data packet, the packet descriptor containing a reference to a memory location of its analyzed data packet stored in the memory;

placing the packet descriptor in a priority queue corresponding to the priority class of the data packet;

arbitrating and selecting a packet descriptor from among the priority queues using selection logic implementing a queue scheme;

reading a data packet corresponding to the selected packet descriptor from the memory; and

sending the data packets read from the memory to the second processor as an aggregated data stream.

31. The method of claim 30, wherein said analyzing and classifying comprises:

protocol-filtering to determine if the ingress data packet is a certain protocol packet.

32. The method of claim 31, wherein the at least one priority factor comprises:

protocol filter priority;

per-port priority; and

virtual LAN priority.

33. The method of claim 30, wherein said analyzing comprises:

decoding a header of each ingress data packet to extract the at least one priority factor.

34. The method of claim 30, further comprising:

buffering the analyzed data packet in a write buffer before storing in the memory.

35. The method of claim 34, further comprising:

asserting a flow control signal if an amount of data stored in the write buffer exceeds a threshold.

36. The method of claim 30, further comprising:

buffering the data packet read from the memory in a read buffer.

37. The method of claim 30, further comprising:

encoding the data packets into an interface format before sending to the second processor.

38. The method of claim 30, further comprising:

asserting a flow control signal if a length of a corresponding priority queue exceeds a threshold.

39. The method of claim 30, wherein said memory is an external buffer memory.

40. The method of claim 30, wherein each of the first processors and the second processor transmits and receives a data stream through a logical interface providing logical interconnection between a Media Access Control sublayer (MAC) and a Physical layer (PHY).

41. The method of claim 30, wherein said analyzing and classifying, said generating, and said storing are performed separately for each data stream.

42. The method of claim 30, wherein, in said placing, the packet descriptors from each data stream of a same priority class are placed in the same priority queue for that priority class.

43. The method of claim 30, wherein said arbitrating and selecting, said reading, and said sending are performed as a single data channel.

44. A method for aggregating data packets, said method comprising:

receiving an input data stream from a first processor via a first data link having a first bandwidth, the input data stream comprising ingress data packets, each ingress data packet comprising at least one priority factor coded therein;

generating an aggregated data stream by analyzing and selectively recombining the ingress data packets in response to the at least one priority factor, the at least one priority factor comprising an indication of whether the ingress packet contains protocol data or not;

generating a packet descriptor for the analyzed ingress data packet, the packet descriptor containing a reference to a memory location of its analyzed data packet stored in a memory; and

outputting the aggregated data stream to a second processor via a second data link having a second bandwidth, wherein the first bandwidth is greater than the second bandwidth.

45. The method of claim 44 wherein analyzing the ingress data packets comprises decoding a header of each ingress data packet to extract the at least one priority factor.

46. The method of claim 44 further comprising:

encoding the aggregated data packets into an interface format before sending to the second processor.

47. The method of claim 44 wherein analyzing the ingress data packets is performed separately for each data stream.

48. A method for aggregating a plurality of input data streams from first processors into one data stream for a second processor, said method comprising:

providing, for each first processor, an analyzer corresponding to the first processor, the analyzer being separate from the first processor and located in a communication path between the first processor and the second processor;

receiving an input data stream from each of the first processors, each input data stream comprising ingress data packets, each ingress data packet comprising at least one priority factor coded therein;

generating an aggregated data stream by combining the plurality of input data streams into one aggregated data stream in response to the at least one priority factor, the at least one priority factor comprising an indication of whether the ingress packet contains protocol data or not, wherein the generating comprises, for each first processor, receiving the input data stream from the first processor at an analyzer corresponding to the first processor, and analyzing the input data stream received from the first processor using the analyzer to classify each of the ingress data packets into one of a plurality of priority classes based on the at least one priority factor;

generating a packet descriptor for the ingress data packet, the packet descriptor containing a reference to a memory location of its ingress data packet stored in a memory; and

outputting the aggregated data stream to the second processor.

49. A system comprising:

an input interface having a first bandwidth and configured to receive a data stream, wherein the data stream comprises ingress data packets, each ingress data packet comprising at least one priority factor coded therein;

a module coupled to the input and configured to receive the data stream, analyze the data stream and selectively recombine the ingress data packets in response to the at least one priority factor, the at least one priority factor comprising an indication of whether the ingress packet contains protocol data or not; and

an output interface having a second bandwidth having a second bandwidth and configured to output the recombined ingress data packets;

wherein the first bandwidth is greater than the second bandwidth;

wherein the module is further configured to generate a packet descriptor for the analyzed ingress data packet, the packet descriptor containing a reference to a memory location of its analyzed data packet stored in a memory.

50. The system of claim 49 wherein configured to analyze the ingress data packets further comprises configured to decode a header of each ingress data packet to extract the at least one priority factor.

51. The system of claim 49 further comprising an encoder configured to encode the recombined ingress data packets into an interface format before sending to a processor.

52. The system of claim 49 wherein each ingress data packets is analyzed separately.

53. A system for aggregating data packets, said system comprising:

a means for receiving an input data stream from a first processor via a first data link having a first bandwidth, the input data stream comprising ingress data packets, each ingress data packet comprising at least one priority factor coded therein;

means for generating an aggregated data stream by analyzing and selectively recombining the ingress data packets in response to the at least one priority factor, the at least one priority factor comprising an indication of whether the ingress packet contains protocol data or not;

means for outputting the aggregated data stream to a second processor via a second data link having a second bandwidth, wherein the first bandwidth is greater than the second bandwidth; and

means for generating a packet descriptor for the analyzed ingress data packet, the packet descriptor containing a reference to a memory location of its analyzed data packet stored in a memory.

54. The system of claim 53 wherein analyzing the ingress data packets comprises a means for decoding a header of each ingress data packet to extract the at least one priority factor.

55. The system of claim 53 further comprising:

means for encoding the aggregated data packets into an interface format before sending to the second processor.

56. The system of claim 53 wherein analyzing the ingress data packets is performed separately for each data stream.