Radio receiver including a delay-locked loop (DLL) for phase adjustment
First Claim
1. A receiver circuit, comprising:
- a) a voltage-controlled oscillator (VCO) configured to provide a reference clock;
b) a delay element configured to receive said reference clock and provide a delay adjustment signal;
c) a first channel configured to receive a radio signal and provide a recovered radio signal from said radio signal and said delay adjustment signal, said first channel comprising a first mixer and a first filter; and
d) a second channel configured to receive said radio signal and a phase adjustment signal derived from said delay adjustment signal, and provide a delay control signal to said delay element from said radio signal and said phase adjustment signal, said second channel comprising a second mixer and a second filter.
2 Assignments
0 Petitions
Accused Products
Abstract
A method, algorithm, architecture, circuits, and/or systems for using a delay-locked loop (DLL) for phase adjustment in a direct conversion radio receiver are disclosed. In one embodiment, a receiver circuit can include: (i) a voltage-controlled oscillator (VCO) for providing a reference clock; (ii) a delay element that can receive the reference clock and provide a delay adjustment signal; (iii) a first channel for receiving a radio signal and providing a recovered radio signal from the radio signal and the delay adjustment signal, where the first channel includes a first mixer and a first filter; and (iv) a second channel for receiving the radio signal and a phase adjustment signal derived from the delay adjustment signal and for providing a delay control signal to the delay element from the radio signal and the phase adjustment signal, where the second channel includes a second mixer and a second filter.
-
Citations
29 Claims
-
1. A receiver circuit, comprising:
-
a) a voltage-controlled oscillator (VCO) configured to provide a reference clock; b) a delay element configured to receive said reference clock and provide a delay adjustment signal; c) a first channel configured to receive a radio signal and provide a recovered radio signal from said radio signal and said delay adjustment signal, said first channel comprising a first mixer and a first filter; and d) a second channel configured to receive said radio signal and a phase adjustment signal derived from said delay adjustment signal, and provide a delay control signal to said delay element from said radio signal and said phase adjustment signal, said second channel comprising a second mixer and a second filter. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
-
-
14. A method of recovering a modulated radio signal, comprising the steps of:
-
a) generating a delay adjustment signal by delaying a reference clock by a configurable delay; b) phase-shifting said delay adjustment signal to provide a phase adjustment signal; c) generating a delay control signal from a received radio signal and said phase adjustment signal; and d) recovering said modulated radio signal from said received radio signal and said delay adjustment signal. - View Dependent Claims (15, 16, 17, 18, 19)
-
-
20. A method of synchronizing a reference clock to a radio signal, comprising the steps of:
-
a) receiving said radio signal in first and second channels, said first channel providing a recovered radio signal using a delay adjustment signal, and said second channel providing a delay control signal using a phase adjustment signal derived from said delay adjustment signal; b) controlling a delay element using said delay control signal, said delay element receiving a reference clock and providing said delay adjustment signal; and c) resetting said delay control signal at a predetermined time. - View Dependent Claims (21, 22, 23, 24, 25, 26)
-
-
27. A circuit for resetting a delay in a delay-locked loop (DLL), comprising:
-
a channel configured to receive a radio signal and provide a delay control signal from said radio signal and a phase adjustment signal, said channel comprising a mixer and a filter, wherein said phase adjustment signal is derived from a delay adjustment signal, and wherein said DLL comprises a delay element configured to provide said delay adjustment signal from a reference clock; and a reset circuit configured to reset said delay control signal at a predetermined time; wherein said reset circuit comprises; a) first and second replica delay lines; and b) a comparator coupled to an output of said filter and an output of said second replica delay line, wherein said comparator is configured to generate a pulse for resetting a switch to reset said delay control signal to a value of a delay control for said first replica delay line, said pulse being generated when an output of said first replica delay line has a cos(0) value, and an output of said second replica delay line has a cos(2π
) value.
-
-
28. A circuit for resetting a delay in a delay-locked loop (DLL), comprising:
-
a) a channel configured to receive a radio signal and provide a delay control signal from said radio signal and a phase adjustment signal, said channel comprising a mixer and a filter, wherein said phase adjustment signal is derived from a delay adjustment signal, and wherein said DLL comprises a delay element configured to provide said delay adjustment signal from a reference clock; and b) a reset circuit configured to reset said delay control signal at a predetermined time; wherein said reset circuit comprises a switch coupled to said filter, said switch being configured to reset said filter at said predetermined time. - View Dependent Claims (29)
-
Specification