Multi-chip systems using on-chip photonics

• US 7,817,880 B1
• Filed: 03/26/2007
• Issued: 10/19/2010
• Est. Priority Date: 03/28/2006
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Oracle America, Inc. (Oracle Corporation)
• Inventors: Cunningham, John E., Krishnamoorthy, Ashok V., Drost, Robert J., Ho, Ronald
• Primary Examiner(s): Petkovsek; Daniel
• Application Number:
  US11/728,845
• Time in Patent Office: 1,303 Days
• Field of Search: 385/14, 385129-132, 398128-131, 398/135, 398138-141, 398/156
• US Class Current: 385/14
• CPC Class Codes: G02B 6/35 having switching means by changing the optical properties of the medium G02F1/00
• CPC Class Codes: G02B 6/43 Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
• CPC Class Codes: H04B 10/803 Free space interconnects, e.g. between circuit boards or chips

Abstract

Embodiments of a system are described. This system includes an array of single-chip modules (CMs), which includes a first CM and a second CM which are coupled to each other. A given CM, which can be either the first CM or the second CM, includes a semiconductor die that is configured to communicate data signals with other CMs by capacitively coupled proximity communication and optical proximity communication using proximity connectors. These proximity connectors are proximate to a surface of the semiconductor die, and the semiconductor die includes an optical signal path configured to communicate on-chip optical signals.

Claims

1. A system, comprising an array of chip modules (CMs), wherein the array includes:

a first CM; and

a second CM coupled to the first CM, wherein the first CM and the second CM each include a semiconductor die that is configured to communicate data signals using capacitively coupled proximity communication and optical proximity communication using proximity connectors, wherein the proximity connectors are proximate to a surface of each semiconductor die, wherein each semiconductor die includes an optical signal path configured to communicate on-chip signals;

wherein at least one of the semiconductor chips is configured to communicate control and data signals separately in a corresponding one of the optical signal path and an electrical signal path coupled to the capacitively coupled proximity connectors;

wherein the first CM and the second CM communicate data signals with each other using capacitively coupled proximity communication and optical proximity communication using the proximity connectors.

2. The system of claim 1, wherein the surface of the semiconductor die in the first CM faces the surface of the semiconductor die in the second CM so that proximity connectors on the semiconductor die in the first CM are coupled to proximity connectors on the semiconductor die in the second CM, thereby facilitating the proximity communication between the first CM and the second CM.

3. The system of claim 1, wherein the system further includes:

a bridge component that includes two sets of proximity connectors and a set of wires, wherein the set of wires is configured to electrically connect a proximity connector in a first of the sets of proximity connectors to a proximity connector in a second of the sets of proximity connectors;

wherein proximity connectors on the semiconductor die in the first CM are coupled to proximity connectors on the semiconductor die in the second CM via a bridge component, thereby facilitating the proximity communication between the first CM and the second CM.

4. The system of claim 1, wherein the proximity connectors in one or more of the semiconductor dies are proximate to a corner of the semiconductor die.

5. The system of claim 1, wherein the proximity connectors in one or more of the semiconductor dies are proximate to a side of the semiconductor die.

6. The system of claim 1, wherein a communication bandwidth between the first CM and a group of CMs in the system approximately equals a total bandwidth associated with a single-chip implementation of the first CM and the group of CMs;

wherein the group of CMs includes the second CM; and

wherein the group of CMs are adjacent to the first CM.

7. The system of claim 1, wherein optical communication of the on-chip optical signals via the optical signal path has a latency less than a pre-determined value.

8. The system of claim 1, wherein one or more of the semiconductor dies includes a conversion element configured to convert electrical signals received from an adjacent CM via capacitively coupled proximity communication into the on-chip optical signals.

9. The system of claim 8, wherein one or more of the semiconductor dies are coupled to an optical source, and wherein the conversion element in the semiconductor die is configured to modulate the optical source during the conversion.

10. The system of claim 1, wherein one or more of the semiconductor dies includes a conversion element configured to convert the on-chip optical signals into electrical signals for communication with an adjacent CM via capacitively-coupled proximity communication.

11. The system of claim 10, wherein one or more of the semiconductor dies is coupled to an optical source, and wherein the conversion element is configured to modulate the optical source during the conversion.

12. The system of claim 1, wherein the optical signal path includes an optical waveguide.

13. The system of claim 1, wherein the optical signal path is routed proximate to a periphery of a cross-section of the semiconductor die.

14. The system of claim 1, wherein the optical signal path is routed proximate to a center of a cross-section of the semiconductor die.

15. The system of claim 1, wherein communication of the on-chip optical signals includes encoding of information using time-division multiple access, frequency-division multiple access, or code-division multiple access.

16. The system of claim 1, wherein communication of the on-chip optical signals uses wavelength-division multiplexing.

17. The system of claim 1, wherein at least one of the semiconductor dies includes a processor core, wherein the semiconductor die includes a conversion element configured to convert first on-chip optical signals into first electrical signals to be processed in the processor core, and wherein, after processing, the conversion element is configured to convert second electrical signals into second on-chip optical signals.

18. The system of claim 1, wherein at least one of the semiconductor dies includes a memory core, wherein the semiconductor die includes a conversion element configured to convert the on-chip optical signals into electrical signals to be stored in the memory core, and wherein, after storage, the conversion element is configured to convert the electrical signals into the on-chip optical signals.

19. The system of claim 1, wherein the on-chip optical signals include synchronization signals.