Architecture for dynamically reconfigurable system-on-chip arrangements, related methods and computer program product

• US 7,818,163 B2
• Filed: 04/11/2006
• Issued: 10/19/2010
• Est. Priority Date: 04/11/2005
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Lertora, Francesco, Borgatti, Michele
• Primary Examiner(s): FREJD, RUSSELL WARREN
• Application Number:
  US11/402,281
• Publication Number:
  US 20070088537A1
• Time in Patent Office: 1,652 Days
• Field of Search: 703/28, 716/12, 716/16, 326/41, 718/100
• US Class Current: 703/28
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture

Abstract

A system-on-chip arrangement having, in possible combination with a processor, a plurality of reconfigurable gate array devices, and a configurable Network-on-Chip connecting the gate array devices to render the arrangement scalable. The arrangement lends itself to be operated by mapping in one device of the gate array a set of processing modules, and configuring another device of the plurality of gate array devices as a microcontroller having stored therein software code portions for controlling inter-operation of the processing modules stored in the one device of the plurality. The arrangement is thus adapted, e.g., to handle different computational granularity levels.

Claims

1. A system-on-chip arrangement, comprising:

a plurality of reconfigurable gate array devices;

a configurable Network-on-Chip connecting said plurality of gate array devices and using versatile message interfaces for each of the plurality of gate array devices to render said arrangement scalable, the versatile message interfaces configured for arbitration and communication between the plurality of gate array devices and the Network-on-Chip; and

a processor for interoperation with said plurality of gate array devices, said processor comprising an ARM-based processor.

2. The arrangement of claim 1 wherein said gate array devices comprise Field-Programmable Gate Arrays.

3. The arrangement of claim 2 wherein said Field-Programmable Gate Arrays are embedded Field-Programmable Gate Arrays.

4. The arrangement of claim 1, comprising at least one additional gate array device for interoperation with said processor and a bus arrangement for connecting said at least one additional device to said processor.

5. A system-on-chip arrangement, comprising:

a plurality of configurable gate array devices connected to a configurable Network-on-Chip via versatile message interfaces to render the arrangement configurable, wherein the versatile message interfaces are configured to perform at least one of the functions selected out of;

arbitration in communication between said gate array devices and said Network-on-Chip, and

packetizing the information exchanged between said gate array devices and said Network-on-Chip,

the versatile message interfaces configured to perform at least one of the functions selected out of;

decoding and forwarding the packets from said Network-on-Chip to said gate array devices,

setting up a communication channel upon request from one of said gate array devices, and

automatically recognizing if a hardware process is interfaced with any of said gate array devices.

6. The arrangement of claim 5, comprising one respective versatile message interface for each of said gate array devices.

7. The arrangement of claim 5 wherein at least a part of said gate array devices are coupled with a register file to avoid mapping of single registers.

8. The arrangement of claim 7, comprising a processor for interoperation with said plurality of gate array devices and in that at least one of said gate array devices has a dedicated link to said processor.

9. The arrangement of claim 8 wherein said gate array devices define a reconfigurable platform configured for packet-based/message-based communication and the arrangement includes a set of interfaces for coupling the reconfigurable platform with the system-on-chip.

10. A method of operating an arrangement including a plurality of reconfigurable gate array devices, a configurable Network-on-Chip connecting the plurality of reconfigurable gate array devices to render said arrangement scalable, a dual port RAM that is accessed at the same time by multiple reconfigurable gate array devices;

and a processor for interoperation with said plurality of gate array devices, the method including the steps of;

fetching processing modules from the dual port RAM for at least one of the plurality of gate array devices;

mapping in one gate array device of the plurality of gate array devices a set of processing modules in the processor, and

configuring another gate array device of the plurality of reconfigurable gate array devices as a microcontroller having stored therein software code portions for controlling inter-operation of the set of processing modules stored in the one gate array device of the plurality of reconfigurable gate array devices.

11. The method of claim 10, comprising the step of said another gate array device of said plurality of gate array devices downloading therein said software code portions for controlling inter-operation of said processing modules stored in said one gate array device of said plurality.

12. The method of claim 10, comprising the step of identifying said processing modules stored in the one gate array device as coarse-grain computational resources.

13. The method of claim 12, comprising the steps of:

identifying said processing modules stored in said one gate array device as a function of the processing module granularity of at least one given application computational kernel, and

configuring the microcontroller having stored therein software code portions for controlling inter-operation of said processing modules stored in said one device of said plurality of field programmable gate array devices to execute said at least one given application computational kernel.

14. The method of claim 13, comprising the steps of configuring in said plurality of gate array devices microcontrollers having stored therein respective sets of software code portions for controlling inter-operation of said processing modules stored in said one gate array device to execute computational kernels of different computational granularity.

15. A microcontroller architecture configured within a reconfigurable gate array device where used microcode is fetched from a dedicated program memory in the form of a dual port RAM that is accessed at the same time by multiple reconfigurable gate array devices.

16. The microcontroller architecture of claim 15 wherein the microcontroller is configured for controlling reconfigurable coarse grain modules.

17. The microcontroller architecture of claim 15 wherein the dual port RAM is accessed at the same time by the reconfigurable gate array devices and from a system-on-chip.

18. A computer readable medium containing software instructions that when executed cause a computer system to reconfigure a system-on-chip by performing a method that comprises the steps of:

mapping in one gate array device of said plurality of gate array devices a set of processing modules;

configuring another gate array device of said plurality of gate array devices as a microcontroller having stored in a memory therein software code portions for controlling inter-operation of said processing modules stored in said one gate array device of said plurality of gate array devices; and

accessing the memory at the same time by the plurality of gate array devices and the system-on-chip.

19. The computer readable medium of claim 18, comprising the step of said another gate array device of said plurality of gate array devices downloading therein said software code portions for controlling inter-operation of said processing modules stored in said one gate array device of said plurality of gate array devices.

20. The computer readable medium of claim 18, comprising the step of identifying said processing modules stored in said one gate array device of said plurality of gate array devices as coarse-grain computational resources.

21. The computer readable medium of claim 20, comprising the steps of:

identifying said processing modules stored in said one device of said plurality of gate array devices as a function of the processing module granularity of at least one given application computational kernel, and

configuring the microcontroller having stored therein software code portions for controlling inter-operation of said processing modules stored in said one device of said plurality of field programmable gate array devices to execute said at least one given application computational kernel.

22. The computer readable medium of claim 21, comprising the steps of configuring in said plurality of gate array devices microcontrollers having stored therein respective sets of software code portions for controlling inter-operation of said processing modules stored in said one device of said plurality of field programmable gate array devices to execute computational kernels of different computational granularity.

23. A circuit, comprising:

a plurality of field-programmable gate array devices coupled to a processor for interoperation of said plurality of gate array devices, the processor comprising an ARM-based processor; and

a configurable network-on-chip connecting the plurality of gate array devices to enable a scalable arrangement, the network-on-chip coupled to the field programmable gate array devices via versatile message interfaces for each of the plurality of gate array devices, the versatile message interfaces configured for arbitration and communication between the plurality of field programmable gate array devices and the network-on-chip.

24. The circuit of claim 23 wherein the versatile message interfaces are configured to perform packetizing information exchanged between the plurality of field programmable gate array devices and the network-on-chip.

25. A circuit, comprising:

a plurality of field-programmable gate array devices coupled to a processor for interoperation of said plurality of gate array devices, the processor comprising an ARM-based processor; and

a configurable Network-on-Chip connecting the plurality of gate array devices to enable a scalable arrangement, the network-on-chip coupled to the field programmable gate array devices via versatile message interfaces for each of the plurality of gate array devices wherein the versatile message interfaces are configured to perform at least one of the following functions;

decoding and forwarding packets from the network-on-chip to the plurality of field programmable gate array devices;

setting up at least one communication channel upon request from at least one of the plurality of field programmable gate array devices; and

automatically recognizing when a hardware process is interfaced with any of the plurality of gate array devices.

26. The circuit of claim 25 wherein at least a one of the plurality of gate array devices is coupled with a register file to avoid mapping of single registers.

27. The circuit of claim 25 wherein the plurality of field programmable gate array devices define a reconfigurable platform for packet-based/message-based communication, and further comprising a set of interfaces for coupling the reconfigurable platform with the network-on-chip.