Direct digital synthesizer, direct digital synthesizer for transmission and detection, and MRI apparatus
First Claim
1. A direct digital synthesizer for transmission and detection, comprising:
- a transmitting phase accumulator for outputting phase data (P1) with a clock frequency f1;
a transmitting waveform LUT for outputting transmitting signal amplitude data (T) in accordance with said phase data (P1);
a curtailing device for outputting phase data (P2) with a clock frequency f2 (<
f1) by implementing curtailing process to said phase data (P1) and also outputting additional data (A) for compensating for phase information disappeared with said curtailing process;
wherein said additional data (A) is assigned the binary value indicating which phase region said phase data (P2) belongs according to ‘
00’
=0°
to 360°
, ‘
01’
=360°
to 720°
, ‘
10’
=−
360°
to −
720°
, and ‘
11’
=−
360°
to 0° and
said additional data (A) is assigned according to 360°
times an integer where ‘
00’
is integer 0, ‘
01’
is integer 2, ‘
10’
is integer −
2, and ‘
11’
is integer −
1;
an interpolating device for outputting phase data (P3) with a clock frequency f3 (>
f2) by implementing interpolating process in accordance with said phase data (P2) and said additional data (A) outputted from said curtailing device;
and a detecting waveform LUT for outputting detecting signal amplitude data (S) in accordance with said phase data (P3) outputted from said interpolating device.
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0 Petitions
Accused Products
Abstract
In order to output amplitude data with the clock frequency higher than the clock frequency of phase data, the direct digital synthesizer for transmission and detection comprises: a transmitting phase for outputting a first phase data with a first clock frequency; a curtailing unit for outputting a second phase data with a second clock frequency smaller than the first clock frequency, and outputting additional data for compensating for phase information disappeared with curtailing process; an interpolating unit for outputting a third phase data with a third clock frequency larger than the first frequency by implementing interpolating process to the second phase data, and a detecting waveform for outputting amplitude data in accordance with the third phase data. The detecting signal amplitude data can be outputted with the third clock frequency higher than the second clock frequency of the second phase data transmitted.
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Citations
18 Claims
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1. A direct digital synthesizer for transmission and detection, comprising:
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a transmitting phase accumulator for outputting phase data (P1) with a clock frequency f1; a transmitting waveform LUT for outputting transmitting signal amplitude data (T) in accordance with said phase data (P1); a curtailing device for outputting phase data (P2) with a clock frequency f2 (<
f1) by implementing curtailing process to said phase data (P1) and also outputting additional data (A) for compensating for phase information disappeared with said curtailing process;wherein said additional data (A) is assigned the binary value indicating which phase region said phase data (P2) belongs according to ‘
00’
=0°
to 360°
, ‘
01’
=360°
to 720°
, ‘
10’
=−
360°
to −
720°
, and ‘
11’
=−
360°
to 0° and
said additional data (A) is assigned according to 360°
times an integer where ‘
00’
is integer 0, ‘
01’
is integer 2, ‘
10’
is integer −
2, and ‘
11’
is integer −
1;an interpolating device for outputting phase data (P3) with a clock frequency f3 (>
f2) by implementing interpolating process in accordance with said phase data (P2) and said additional data (A) outputted from said curtailing device;and a detecting waveform LUT for outputting detecting signal amplitude data (S) in accordance with said phase data (P3) outputted from said interpolating device. - View Dependent Claims (2, 3, 14)
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4. A direct digital synthesizer for transmission and detection, comprising:
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a transmitting phase accumulator for outputting phase data (P1) with a clock frequency 1; a transmitting waveform LUT for outputting transmitting signal amplitude data (T) in accordance with said phase data (P1); a difference phase accumulator for outputting difference phase data (A1) with the clock frequency f1; an adding device for outputting phase data (P1′
) with the clock frequency f1 by adding said phase data (P1) and said difference phase data (A1);a curtailing device for outputting phase data (P2) with a clock frequency f2 (<
f1) by implementing curtailing process to said phase data (P1′
) outputted from said adding device and also outputting additional data (A) for compensating for phase information disappeared with said curtailing process;wherein said additional data (A) is assigned the binary value indicating which phase region said phase data (P2) belongs according to ‘
00’
=0°
to 360°
, ‘
01’
=360°
to 720°
, ‘
10’
=−
360°
to −
720°
, and ‘
11’
=−
360°
to 0° and
said additional data (A) is assigned according to 360°
times an integer where ‘
00’
is integer 0, ‘
01’
is integer 2, ‘
10’
is integer −
2, and ‘
11’
is integer −
1;an interpolating device for outputting phase data (P3) with a clock frequency f3 (>
f2) by implementing interpolating process in accordance with said phase data (P2) and said additional data (A) outputted from said curtailing device;and a detecting waveform LUT for outputting detecting signal amplitude data (S) in accordance with said phase data (P3) outputted from said interpolating device. - View Dependent Claims (5, 6, 17)
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7. A direct digital synthesizer for transmission and detection, comprising:
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a transmitting phase accumulator for outputting phase data (P1) with a clock frequency f1; a transmitting waveform LUT for outputting transmitting signal amplitude data (T) in accordance with said phase data (P1); a curtailing device for outputting phase data (P2) with a clock frequency f2 (<
f1) by implementing curtailing process to said phase data (P1) and also outputting additional data (A) for compensating for phase information disappeared with said curtailing process;wherein said additional data (A) is assigned the binary value indicating which phase region said phase data (P2) belongs according to ‘
00’
=0°
to 360°
, ‘
01’
=360°
to 720°
, ‘
10’
=−
360°
to −
720°
, and ‘
11’
=−
360°
to 0° and
said additional data (A) is assigned according to 360°
times an integer where ‘
00’
is integer 0, ‘
01’
is integer 2, ‘
10’
is integer −
2, and ‘
11’
is integer −
1;a difference outputting device for outputting difference data (V2) of said phase data (P2);
an absolute value outputting device for recovering and outputting said phase data (P2) from said difference data (V2);an interpolating device for outputting phase data (P3) with a clock frequency f3 (>
f2) by implementing interpolating process in accordance with said phase data (P2) and said additional data (A) outputted from said absolute value outputting device;and a detecting waveform LUT for outputting detecting signal amplitude data (S) in accordance with said phase data (P3) outputted from said interpolating device. - View Dependent Claims (8, 9, 13, 15)
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10. A direct digital synthesizer for transmission and detection, comprising:
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a transmitting phase accumulator for outputting phase data (P1) with a clock frequency f1; a transmitting waveform LUT for outputting transmitting signal amplitude data (T) in accordance with said phase data (P1); a difference phase accumulator for outputting difference data (A1) with the clock frequency f1; an adding device for outputting phase data (P1′
) with the clock frequency f1 by adding said phase data (P1) and said difference phase data (A1);an curtailing device for outputting phase data (P2) with a clock frequency f2 (<
f1) by implementing curtailing process to said phase data (P1′
) outputted from said adding device and also outputting additional data (A) for compensating for phase information disappeared with said curtailing process;wherein said additional data (A) is assigned the binary value indicating which phase region said phase data (P2) belongs according to ‘
00’
=0°
to 360°
, ‘
01’
=360°
to 720°
, ‘
10’
=−
360°
to −
720°
, and ‘
11’
=−
360°
to 0° and
said additional data (A) is assigned according to 360°
times an integer where ‘
00’
is integer 0, ‘
01’
is integer 2, ‘
10’
is integer −
2, and ‘
11’
is integer −
1;a difference outputting device for outputting difference data (V2) of said phase data (P2); an absolute value outputting device for recovering and outputting said phase data (P2) from said difference data (V2); an interpolating device for outputting phase data (P3) with a clock frequency f3 (>
f2) by implementing curtailing process in accordance with said phase data (P2) and said additional data (A) outputted from said absolute value outputting device;and a detecting waveform LUT for outputting detecting signal amplitude data (S) in accordance with said phase data (P3) outputted from said interpolating device. - View Dependent Claims (11, 12, 16, 18)
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Specification