Apparatus and method for capturing serial input data

• US 7,818,464 B2
• Filed: 12/06/2006
• Issued: 10/19/2010
• Est. Priority Date: 12/06/2006
• Status: Expired due to Fees

• Current Assignee: NovaChips Canada Inc. (NovaChips Co., Ltd.)
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Oh, HakJune, Pyeon, Hong Beom
• Primary Examiner(s): Kindred; Alford W
• Assistant Examiner(s): TAYLOR, BROOKE JAZMOND
• Application Number:
  US11/567,551
• Publication Number:
  US 20080137467A1
• Time in Patent Office: 1,413 Days
• Field of Search: 710/5
• US Class Current: 710/5
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1093 Input synchronization

Abstract

A serial input processing apparatus provides how to capture serial data without loss of a single bit while command interpretation is being performed in a command decoder at high frequency. Individual bytes of serial bits of a pre-defined sequence are latched and bit streams are temporarily stored with multiple clocks. The temporary store is conducted before transferring byte information to assigned address registers to register the address. The address registration and the data registration are performed by latching all bit streams of the serial input at the leading edges of clocks. While at a high frequency operation (e.g., 1 GHz or 1 ns cycle time), no additional registers are required for storing bit data during command interpretation with enough time margins between the command bit stream interpretation and next bit data stream.

Claims

1. A method for processing a serial input (SI) including command, address and data in accordance with a pre-defined sequence and grouped as bit streams representing the command address and data, the method comprising:

receiving the SI;

holding the bit streams of the received SI by temporarily storing the bit stream representing the address in the received SI;

interpreting the command of the received SI by storing the command of the received SI, and decoding the stored command to determine an operation control mode of the command, the command being interpreted independently of holding the bit streams and during the step of holding being conducted;

accessing a memory in response to the interpreted command and based on the temporarily stored address;

receiving an input enable (IPE) to enable receiving of the command of the SI;

producing operation clocks locally in response to an input clock that relates to the bit stream by producing a first clock in response to the input clock and the input enable, the first clock being used for interpreting the command;

producing a second clock in response to the input clock and the operation control mode, independently of the first clock, the second clock being used for holding the bit streams;

and, producing a third clock in response to the input clock and the operation control mode, the third clock being used for holding the bit streams relating to the data;

ceasing the production of the first clock;

ceasing the production of the second clock after the ceasing production of the first clock, in accordance with the determined operation control mode;

and ceasing the production of the third clock after the ceasing of production of the second clock, in accordance with the determined operation control mode.

6. The method of claim 1, wherein the step of producing a second clock comprises:

producing the second clock in response to the received input enable i˜

; and

the step of producing a third clock comprises;

producing the third clock in response to the received input enable.

7. The method of claim 1, wherein the step of producing a second clock comprises:

producing the second clock upon completion of ceasing the production of the first clock; and

the step of producing a third clock comprises;

producing the third clock upon completion of ceasing the production of the first clock.

2. The method of claim, wherein the step of accessing comprises:

capturing the data of the received SI;

and the step of holding comprises;

transferring the temporarily stored address for accessing the memory based on the captured data.

3. The method of claim 2, wherein the step of transferring comprises establishing a path of the temporarily stored address in response to the operation control mode, so as to transfer the temporarily stored address therethrough.

4. The method of claim 3, further comprising providing transfer path information according to the operation control mode, the transfer path information being used for establishing a path of the temporarily stored address.

5. The method of claim 2, wherein the step of transferring comprises transferring the temporarily stored address through a pre-defined path.