Buffered memory module supporting two independent memory channels
First Claim
Patent Images
1. A memory system, comprising:
- a memory controller; and
a memory module coupled to the memory controller, wherein the memory controller is coupled to the memory module via at least two independent memory channels, and wherein the at least two independent memory channels are coupled to one or more memory hub devices of the memory module, wherein the memory module comprises a single memory hub device, wherein both of the at least two independent memory channels are coupled to the single memory hub device of the memory module, wherein the single memory hub device comprises four separate memory device data interfaces for communicating with four separate sets of memory devices, wherein a first memory channel of the at least two independent memory channels is coupled to a first memory device data interface and a second memory device data interface, and wherein a second memory channel of the at least two independent memory channels is coupled to a third memory device data interface and a fourth memory device data interface.
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Abstract
A memory system is provided that enhances the memory bandwidth available through a memory module. The memory system includes a memory controller and a memory module coupled to the memory controller. In the memory system, the memory controller is coupled to the memory module via at least two independent memory channels. In the memory system, the at least two independent memory channels are coupled to one or more memory hub devices of the memory module.
143 Citations
19 Claims
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1. A memory system, comprising:
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a memory controller; and a memory module coupled to the memory controller, wherein the memory controller is coupled to the memory module via at least two independent memory channels, and wherein the at least two independent memory channels are coupled to one or more memory hub devices of the memory module, wherein the memory module comprises a single memory hub device, wherein both of the at least two independent memory channels are coupled to the single memory hub device of the memory module, wherein the single memory hub device comprises four separate memory device data interfaces for communicating with four separate sets of memory devices, wherein a first memory channel of the at least two independent memory channels is coupled to a first memory device data interface and a second memory device data interface, and wherein a second memory channel of the at least two independent memory channels is coupled to a third memory device data interface and a fourth memory device data interface. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A data processing system, comprising:
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a processor; and a memory controller coupled to the to the processor; a memory module coupled to the memory controller wherein the memory controller is coupled to the memory module via at least two independent memory channels, and wherein the at least two independent memory channels are coupled to one or more memory hub devices of the memory module, wherein the memory module comprises a single memory hub device wherein both of the at east two independent memory channels are coupled to the single memory hub device of the memory module, wherein the single memory hub device comprises four separate memory device data interfaces for communicating with four separate sets of memory devices, wherein a first memory channel of the at least two independent memory channels is coupled to a first memory device data interface and a second memory device data interface, and wherein a second memory channel of the at least two independent memory channels is coupled to a third memory device data interface and a fourth memory device data interface. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A method of accessing memory devices of a memory module, comprising:
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receiving, in one or more memory hub devices integrated in the memory module, an access request for accessing a portion of one of a first set of memory devices or a second set of memory devices integrated in the memory module, wherein the access request is received from a memory controller coupled to the memory module, wherein the memory controller is coupled to the memory module via at least two independent memory channels, and wherein the at least two independent memory channels are coupled to the one or more memory hub devices of the memory module, wherein the memory module comprises a single memory hub device, wherein both of the at least two independent memory channles are coupled to the single memory hub device of the memory module wherein the single memory hub device comprises four separate memory device data interfaces for communicating with four separate sets of memory devices, wherein a first memory channel of the at least two independent memory channels is coupled to a first memory device data interface and a second memory device data interface, and wherein a second memory channel of the at least two independent memory channels is coupled to a third memory device data interface and a fourth memory device data interface; selecting one of the first memory device, data interface, the second memory device data interface, the third memory device data interface, or the fourth memory device data interface integrated in the single memory hub device, for performance of the access request; and accessing one of four separate sets of memory devices in the memory module based on the selected first memory device data interface, the second memory device data interface, the third memory device data interface, or the fourth memory device data interface. - View Dependent Claims (15, 16, 17, 18, 19)
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Specification