Timeslot arbitration scheme

• US 7,818,519 B2
• Filed: 12/02/2003
• Issued: 10/19/2010
• Est. Priority Date: 12/02/2002
• Status: Expired due to Fees

• Current Assignee: Memjet Technology Ltd. (Memjet Limited)
• Original Assignee: Silverbrook Research Pty Limited
• Inventors: Plunkett, Richard Thomas
• Primary Examiner(s): Tsai; Sheng-Jen
• Assistant Examiner(s): Chrzanowski; Matthew R
• Application Number:
  US10/727,157
• Publication Number:
  US 20050177633A1
• Time in Patent Office: 2,513 Days
• Field of Search: 711/158
• US Class Current: 711/158
• CPC Class Codes: B41J 2/04505 aiming at correcting alignment
• CPC Class Codes: B41J 2/04508 aiming at correcting other parameters
• CPC Class Codes: B41J 2/0451 for detecting failure, e.g. clogging, malfunctioning actuator
• CPC Class Codes: B41J 2/04528 aiming at warming up the head
• CPC Class Codes: B41J 2/04541 Specific driving circuit
• CPC Class Codes: B41J 2/04543 Block driving
• CPC Class Codes: B41J 2/04563 detecting head temperature; Ink temperature
• CPC Class Codes: B41J 2/04573 Timing; Delays
• CPC Class Codes: B41J 2/04586 controlling heads of a type not covered by groups B41J2/04575 - B41J2/04585, or of an undefined type
• CPC Class Codes: B41J 2202/20 Modules
• CPC Class Codes: G06F 21/554 involving event detection and direct action
• CPC Class Codes: G06F 21/57 Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
• CPC Class Codes: G06F 21/575 Secure boot
• CPC Class Codes: G06F 21/64 Protecting data integrity, e.g. using checksums, certificates or signatures
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 21/73 by creating or determining hardware identification, e.g. serial numbers
• CPC Class Codes: G06F 21/74 operating in dual or compartmented mode, i.e. at least one secure mode
• CPC Class Codes: G06F 21/78 to assure secure storage of data address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00
• CPC Class Codes: H03K 5/1252 Suppression or limitation of noise or interference specially adapted for transmission systems H04B15/00, H04L25/08
• CPC Class Codes: H04N 1/405 Halftoning, i.e. converting the picture signal of a continuous-tone original into a corresponding signal showing only two levels
• CPC Class Codes: Y10S 707/99933 : Query processing, i.e. searching
• CPC Class Codes: Y10S 707/99939 : Privileged access
• CPC Class Codes: Y10T 29/49401 : Fluid pattern dispersing device making, e.g., ink jet

Abstract

A method for arbitrating between a plurality of access requests issued in relation to a resource by a plurality of requestors, wherein each request can be one of at least two types, a first of the types having a higher latency associated with its performance than at least some of the other types, the method including the steps of: (a) receiving a plurality of the access requests; (the requests are not placed anywhere, they are simply received); (b) maintaining a current pointer that points to a current timeslot in a timeslot list, and at least one lookahead pointer that points to a future timeslot in the timeslot list; and (c) in the event an access request as arbitrated via the lookahead pointer is of the first type, initiating performance of the access request earlier than the position in the list suggests it would be performed should it be started when the current pointer reached the timeslot.

Claims

1. A method for arbitrating between a plurality of access requests issued in relation to a resource by a plurality of requestors in an integrated circuit, wherein each request can be one of a CPU write request from a CPU requester, a non-CPU write request from a non-CPU requester and a non-CPU read request from a non-CPU requester, the method including the steps of:

(a) receiving, in a timeslot arbitrator of the integrated circuit, a plurality of the access requests;

(b) maintaining, in the timeslot arbitrator, a current pointer that points to a current timeslot in a timeslot list, and at least one lookahead pointer that points to a future timeslot in the timeslot list; and

(c) in the event an access request as arbitrated via the lookahead pointer is a non-CPU write request, initiating performance of the access request, in the timeslot arbitrator, earlier than the position in the list suggests it would be performed should it be started when the current pointer reached the current timeslot,

wherein, in step (c), the earlier position is selected so as to not be adjacent a position in the list for performance of another non-CPU write request, and

each timeslot in the timeslot list is configured with a CPU access preceding a non-CPU access so that a CPU write request is performed before either a non-CPU write request or non-CPU read request.

2. A method according to claim 1, wherein step (c) includes the substep of performing the access request indicated by the lookahead pointer immediately after the access request indicated by the current pointer is performed.

3. A method according to claim 1, wherein step (c) includes the timeslot arbitrator arbitrating in the timeslot list CPU write requests to be interleaved with non-CPU write and read requests.

4. A method according to claim 3, wherein step (c) includes the substep of performing the access request indicated by the lookahead pointer immediately after the access request indicated by the current pointer is performed.

5. A method according to claim 1, wherein the number of timeslots between the timeslot indicated by the lookahead pointer and the timeslot indicated by the current pointer takes into account a latency difference between performing the access requests.

6. An integrated circuit including:

a plurality of operative units, each of which is capable of issuing a request for access to a memory accessible by the integrated circuit including a CPU write request from a CPU requester, a non-CPU write request from a non-CPU requester and a non-CPU read request from a non-CPU requester; and

an timeslot arbitrator for arbitrating between requests issued by the operative units for access to the memory, the timeslot arbitrator being configured to;

(a) receive a plurality of the access requests;

(b) maintain a current pointer that points to a current timeslot in a timeslot list, and at least one lookahead pointer that points to a future timeslot in the timeslot list; and

(c) in the event the access request as arbitrated via the lookahead pointer is a non-CPU write request, performing the access request earlier than the position in the list suggests it should be performed should it be started when the current pointer reached the current timeslot,

wherein, in (c), the earlier position is selected so as to not be adjacent a position in the list for performance of another non-CPU write request, and

each timeslot in the timeslot list is configured with a CPU access preceding a non-CPU access so that a CPU write request is performed before either a non-CPU write request or non-CPU read request.

7. An integrated circuit according to claim 6, wherein in (c) the timeslot arbitrator arbitrates, in the timeslot list, CPU write requests to be interleaved with non-CPU write and read requests.

8. An integrated circuit according to claim 6, wherein the number of timeslots between the timeslot indicated by the lookahead pointer and the timeslot indicated by the current pointer takes into account a latency difference between performing the access requests.