Efficient reduction of read disturb errors in NAND FLASH memory

• US 7,818,525 B1
• Filed: 09/24/2009
• Issued: 10/19/2010
• Est. Priority Date: 08/12/2009
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: Texas Memory Systems Incorporated (International Business Machines Corporation)
• Inventors: Frost, Holloway H., Shelton, Lance W., Fisher, Timothy J., Camp, Charles J., Fuxa, James A.
• Primary Examiner(s): Bragdon; Reginald G
• Assistant Examiner(s): Bansal; Gurtej
• Application Number:
  US12/566,421
• Time in Patent Office: 390 Days
• Field of Search: 711/170
• US Class Current: 711/165
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 29/50004 of threshold voltage

Abstract

Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block.

Claims

1. A memory system comprising:

a FLASH memory space organized into a plurality of blocks, each block comprising a plurality of pages, and each page defining an individually addressable physical memory location; and

a controller operatively coupled to the FLASH memory space and configured to;

access a logical-to-physical translation table that associates a logical address provided in a WRITE request with a physical address corresponding to a page within the FLASH memory space;

associate a plurality of blocks together to form a first block group;

associate pages within each of the blocks within the first block group together to form page stripes;

accumulate, for the first block group, a Block Group READ count corresponding to the number of READ requests for a page within any of the blocks within the first block group; and

after the Block Group READ Count for the first block group has reached a predetermined number,

respond to the receipt of a first READ request for a first page within the first block group by moving data associated with the page stripe including the first page to a page stripe in a second block group that is different from the first block group without moving the data from the other page stripes in the first block group to the second block group in response to the receipt of the first READ request; and

respond to the receipt of a second READ request for a second page within the block group by moving data associated with the page stripe including the second page to a block group different from the first block group, without moving the data from the other page stripes in the first block group in response to the receipt of the second READ request.

2. The memory system of claim 1 wherein the controller is configured to initialize the Block Group READ Count for the first block group at a number other than zero.

3. The memory system of claim 1 wherein the controller is further configured to determine whether the Block Group READ Count has reached the predetermined number by determining whether the Block Group READ Count has exceeded a number.

4. The memory system of claim 1 wherein the controller is configured to associate blocks together to form a plurality of block groups and to maintain a Block Group READ Count for each block group within the FLASH memory space.

5. The memory system of claim 1 wherein the controller is configured to provide an indication that a page within the first block group no longer contains valid data upon the movement of the data associated with the page to a page in the second block group.