Method and software for group data operations

• US 7,818,548 B2
• Filed: 07/27/2007
• Issued: 10/19/2010
• Est. Priority Date: 08/16/1995
• Status: Expired due to Fees

• Current Assignee: Microunity Systems Engineering Incorporated
• Original Assignee: Microunity Systems Engineering Incorporated
• Inventors: Moussouris, John, Hansen, Craig, Massalin, Alexia
• Primary Examiner(s): Coleman; Eric
• Application Number:
  US11/878,804
• Publication Number:
  US 20080177986A1
• Time in Patent Office: 1,180 Days
• Field of Search: 712/222
• US Class Current: 712/222
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30029 Logical and Boolean instructions, e.g. XOR, NOT
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30054 Unconditional branch instructions
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/3816 Instruction alignment, e.g. cache line crossing
• CPC Class Codes: G06F 9/3824 : Operand accessing
• CPC Class Codes: G06F 9/383 : Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3861 : Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3873 : Variable length pipelines, e.g. elastic pipeline
• CPC Class Codes: G06F 9/3885 : using a plurality of independent parallel functional units

Abstract

Methods and software are presented for processing data in a programmable processor, involving (a) decoding instructions for execution using an execution unit operable to execute instructions by partitioning data stored in registers in a register file into multiple data elements, the instructions selected from an instruction set that includes group arithmetic instructions and group data handling instructions, (b) in response to decoding different group arithmetic instructions, executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results, and (c) in response to decoding different group data handling instructions, executing group data handling operations that re-arrange data elements in different ways.

Claims

1. A method of processing data in a programmable processor, the method comprising:

decoding instructions for execution using an execution unit coupled to a register file comprising a plurality of registers, the execution unit operable to execute instructions by partitioning data stored in registers in the register file into multiple data elements, the instructions selected from an instruction set that includes group arithmetic instructions and group data handling instructions;

in response to decoding different group arithmetic instructions, executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operate on multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results; and

in response to decoding different group data handling instructions, executing group data handling operations that re-arrange data elements in different ways,

wherein the group data handling instructions include a plurality of swap instructions in which each swap instruction operates on a plurality of equal-sized segments of data in an operand register, the segments being arranged in an order in the operand register, the size of the segments being variable from one swap instruction to another, each segment consisting of a plurality of contiguously arranged, equal-sized data elements, the size of the data elements being variable from one swap instruction to another, each swap instruction reversing the order of the plurality of contiguously arranged data elements within each segment within the operand register, generating segments each consisting of a plurality of contiguously arranged, reverse ordered data elements, the segments being maintained in the same order as they were arranged in the operand register, to produce a catenated result returned to a register in the register file.

2. The method of claim 1 wherein the plurality of swap instructions comprises first, second, third, fourth, fifth, and sixth swap instructions,

wherein for the first swap instruction, the data elements are each 8 bits wide, and the segments are each 16 bits wide,

wherein for the second swap instruction, the data elements are each 8 bits wide, and the segments are each 32 bits wide,

wherein for the third swap instruction, the data elements are each 16 bits wide, and the segments are each 32 bits wide,

wherein for the fourth swap instruction, the data elements are each 8 bits wide, and the segments are each 64 bits wide,

wherein for the fifth swap instruction, the data elements are each 16 bits wide, and the segments are each 64 bits wide, and

wherein for the sixth swap instruction, the data elements are each 32 bits wide, and the segments are each 64 bits wide.

3. The method of claim 1 wherein the group data handling instructions further include a select instruction that operates on a plurality of data elements in a register in the register file and a plurality of indices in another register in the register file, each index selecting one of the plurality of data elements, to provide the data element selected by each index to a predetermined position in a catenated result returned to a register in the register file.

4. The method of claim 3 wherein the group data handling instructions further include a copy instruction that takes a scalar value within a register in the register file and duplicates the scalar value as every data element of a catenated result returned to a register in the register file.

5. The method of claim 4 wherein the group data handling instructions further include a single group shift left instruction specifying a shift amount as an immediate value, capable of causing the execution unit to:

(a) for each of a first plurality of data elements in a register in the register file, shift a subfield of the data element towards the most significant bit by the shift amount, to produce a second plurality of equal-sized data elements, and

(b) provide the second plurality of data elements as a catenated result to a register in the register file, wherein the second plurality of data elements are twice as wide as the first plurality of data elements.

6. The method of claim 5 wherein the group data handling instructions further include a single group shift left instruction specifying an operand register containing a shift amount, capable of causing the execution unit to:

(a) for each of a first plurality of data elements in a register in the register file, shift a subfield of the data element towards the most significant bit by the shift amount, to produce a second plurality of equal-sized data elements, and

(b) provide the second plurality of data elements as a catenated result to a register in the register file.

7. The method of claim 6 wherein the group data handling instructions further include a single group shift right instruction specifying a shift amount as an immediate value, capable of causing the execution unit to:

(a) for each of a first plurality of data elements in a register in the register file, shift a subfield of the data element towards the least significant bit by the shift amount, to produce a second plurality of equal-sized data elements, and

(b) provide the second plurality of data elements as a catenated result to a register in the register file.

8. The method of claim 7 wherein the group data handling instruction further include a single group shift right instruction specifying a shift amount as an immediate value, capable of causing the execution unit to:

(a) for each of a first plurality of data elements in a register in the register file, shift a subfield of the data element towards the least significant bit by the shift amount, to produce a second plurality of equal-sized data elements, and

(b) provide the second plurality of data elements as a catenated result to a register in the register file, wherein the second plurality of data elements are half as wide as the first plurality of data elements.

9. The method of claim 8 wherein the group data handling instructions further include a single group shift instruction specifying a shift amount as an immediate value, capable of causing the execution unit to:

(a) for each of a first plurality of data elements in a first register in the register file, shift a subfield of the data element by the shift amount, to produce a plurality of shifted values, and

(b) insert each of the shifted values into a subfield within one of the second plurality of data elements in a second register in the register file.

10. The method of claim 9 wherein the group data handling instructions further include a shuffle instruction that interleaves a first plurality of data elements from a first register in the register file with a second plurality of data elements from a second register in the register file to produce a catenated result and provides the catenated result to a register in the register file.

11. A computer-readable storage medium:

having instructions stored thereon that instruct a computer system to perform operations using an execution unit coupled to a register file comprising a plurality of registers, by partitioning data stored in registers in the register file into multiple data elements, the instructions selected from an instruction set that includes group arithmetic instructions and group data handling instructions,

the instructions including different group arithmetic instructions for performing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operate on the multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results,

the instructions further including different group data handling instructions that cause the execution unit to re-arrange data elements in different ways,

wherein the group data handling instructions include a plurality of swap instructions in which each swap instruction operates on a plurality of equal-sized segments of data in an operand register, the segments being arranged in an order in the operand register, the size of the segments being variable from one swap instruction to another, each segment consisting of a plurality of contiguously arranged, equal-sized data elements, the size of the data elements being variable from one swap instruction to another, each swap instruction reversing the order of the plurality of contiguously arranged data elements within each segment within the operand register, generating segments each consisting of a plurality of contiguously arranged, reverse ordered data elements, the segments being maintained in the same order as they were arranged in the operand register, to produce a catenated result returned to a register in the register file.

12. The computer-readable storage medium of claim 11 wherein the plurality of swap instructions comprises first, second, third, fourth, fifth, and sixth swap instructions,

wherein for the first swap instruction, the data elements are each 8 bits wide, and the segments are each 16 bits wide,

wherein for the second swap instruction, the data elements are each 8 bits wide, and the segments are each 32 bits wide,

wherein for the third swap instruction, the data elements are each 16 bits wide, and the segments are each 32 bits wide,

wherein for the fourth swap instruction, the data elements are each 8 bits wide, and the segments are each 64 bits wide,

wherein for the fifth swap instruction, the data elements are each 16 bits wide, and the segments are each 64 bits wide, and

wherein for the sixth swap instruction, the data elements are each 32 bits wide, and the segments are each 64 bits wide.

13. The computer-readable storage medium of claim 11 wherein the group data handling instructions further include a select instruction that operates on a plurality of data elements in a register in the register file and a plurality of indices in another register in the register file, each index selecting one of the plurality of data elements, to provide the data element selected by each index to a predetermined position in a catenated result returned to a register in the register file.

14. The computer-readable storage medium of claim 13 wherein the instruction set further includes a copy instruction that takes a scalar value within an operand register and duplicates the scalar value as every data element of a catenated result returned to a destination register.

15. The computer-readable storage medium of claim 14 wherein the group data handling instructions further include single group shift left instruction specifying a shift amount as an immediate value, capable of causing the execution unit to:

(a) for each of a first plurality of data elements in a register in the register file, shift a subfield of the data element towards the most significant bit by the shift amount, to produce a second plurality of equal-sized data elements, and

(b) provide the second plurality of data elements as a catenated result to a register in the register file, wherein the second plurality of data elements are twice as wide as the first plurality of data elements.

16. The computer-readable storage medium of claim 15 wherein the group data handling instructions further include a single group shift left instruction specifying an operand register containing a shift amount, capable of causing the execution unit to:

(a) for each of a first plurality of data elements in a register in the register file, shift a subfield of the data element towards the most significant bit by the shift amount, to produce a second plurality of equal-sized data elements, and

(b) provide the second plurality of data elements as a catenated result to a register in the register file.

17. The computer-readable storage medium of claim 16 wherein the group data handling instructions further include a single group shift right instruction specifying a shift amount as an immediate value, capable of causing the execution unit to:

(a) for each of a first plurality of data elements in a register in the register file, shift a subfield of the data element towards the least significant bit by the shift amount, to produce a second plurality of equal-sized data elements, and

(b) provide the second plurality of data elements as a catenated result to a register in the register file.

18. The computer-readable storage medium of claim 17 wherein the group data handling instructions further include a single group shift right instruction specifying a shift amount as an immediate value, capable of causing the execution unit to:

(a) for each of a first plurality of data elements in a register in the register file, shift a subfield of the data element towards the least significant bit by the shift amount, to produce a second plurality of equal-sized data elements, and

(b) provide the second plurality of data elements as a catenated result to a register in the register file, wherein the second plurality of data elements are half as wide as the first plurality of data elements.

19. The computer-readable storage medium of claim 18 wherein the group data handling instructions further include a single group shift instruction specifying a shift amount as an immediate value, capable of causing the execution unit to:

(a) for each of a first plurality of the data elements in a first register in the register file, shift a subfield of the data element by the shift amount, to produce a plurality of shifted values, and

(b) insert each of the shifted values into a subfield within one of a second plurality of data elements in a second register in the register file.

20. The computer-readable storage medium of claim 19 wherein the group data handling instructions further include a shuffle instruction that interleaves a first plurality of data elements from a first register in the register file with a second plurality of data elements from a second register in the register file to produce a catenated result and provides the catenated result to a register in the register file.