Multi-stage test response compactors
First Claim
1. A circuit for compacting test responses comprising:
- a first spatial compactor comprising a plurality of first-compactor inputs and a first-compactor output;
a register comprising a register input and a plurality of register outputs, the register input being coupled to the first-compactor output, the register being operable to load test response bits through the register input and to output the test response bits in parallel through the plurality of register outputs; and
a second spatial compactor comprising a plurality of second-compactor inputs and a second-compactor output, the plurality of second-compactor inputs being coupled to the plurality of register outputs.
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Accused Products
Abstract
Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.
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Citations
60 Claims
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1. A circuit for compacting test responses comprising:
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a first spatial compactor comprising a plurality of first-compactor inputs and a first-compactor output; a register comprising a register input and a plurality of register outputs, the register input being coupled to the first-compactor output, the register being operable to load test response bits through the register input and to output the test response bits in parallel through the plurality of register outputs; and a second spatial compactor comprising a plurality of second-compactor inputs and a second-compactor output, the plurality of second-compactor inputs being coupled to the plurality of register outputs. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. One or more computer-readable media storing circuit design information for implementing a circuit for compacting test responses, the circuit comprising:
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a first spatial compactor comprising a plurality of first-compactor inputs and a first-compactor output; a register comprising a register input and a plurality of register outputs, the register input being coupled to the first-compactor output, the register being operable to load test response bits through the register input and to output the test response bits in parallel through the plurality of register outputs; and a second spatial compactor comprising a plurality of second-compactor inputs and a second-compactor output, the plurality of second-compactor inputs being coupled to the plurality of register outputs. - View Dependent Claims (18, 19, 20, 21, 22)
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23. One or more computer-readable media storing computer-executable instructions for causing a computer to design a circuit for compacting test responses, the circuit comprising:
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a first spatial compactor comprising a plurality of first-compactor inputs and a first-compactor output; a register comprising a register input and a plurality of register outputs, the register input being coupled to the first-compactor output, the register being operable to load test response bits through the register input and to output the test response bits in parallel through the plurality of register outputs; and a second spatial compactor comprising a plurality of second-compactor inputs and a second-compactor output, the plurality of second-compactor inputs being coupled to the plurality of register outputs. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30)
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31. A method for compacting test responses, comprising:
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compressing a plurality of uncompressed test response bits using a first spatial compactor, thereby producing a first set of compressed test response bits; outputting the first set of compressed test response bits from the first spatial compactor; loading the first set of compressed test response bits into a plurality of sequential elements; unloading in parallel the first set of compressed test response bits from the plurality of sequential elements; further compressing the first set of compressed test response bits using a second spatial compactor after the first set of compressed test response bits are unloaded in parallel from the plurality of sequential elements, thereby producing a second set of compressed test response bits; and outputting the second set of compressed test response bits from the second spatial compactor. - View Dependent Claims (32, 33, 34, 35, 36, 37)
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38. A circuit for compacting test responses comprising:
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two or more sequential elements having respective inputs and outputs, the two or more sequential elements being operable to input a group of two or more uncompressed test response bits through the inputs of the two or more sequential elements and being further operable to output in parallel the group of two or more uncompressed test response bits through the outputs of the two or more sequential elements; a first spatial compactor comprising a plurality of first-compactor inputs and a first-compactor output, the first-compactor inputs being coupled to the outputs of the sequential elements; and a second spatial compactor comprising a plurality of second-compactor inputs and a second-compactor output, one of the plurality of second-compactor inputs being coupled to the first-compactor output. - View Dependent Claims (39, 40, 41, 42, 43, 44, 45, 46, 47)
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48. One or more computer-readable media storing circuit design information for implementing a circuit for compacting test responses, the circuit comprising:
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two or more sequential elements having respective inputs and outputs, the two or more sequential elements being operable to input a group of two or more uncompressed test response bits through the inputs of the two or more sequential elements and being further operable to output in parallel the group of two or more uncompressed test response bits through the outputs of the two or more sequential elements; a first spatial compactor comprising a plurality of first-compactor inputs and a first-compactor output, the first-compactor inputs being coupled to the outputs of the sequential elements; and a second spatial compactor comprising a plurality of second-compactor inputs and a second-compactor output, one of the plurality of second-compactor inputs being coupled to the first-compactor output. - View Dependent Claims (49, 50, 51, 52)
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53. One or more computer-readable media storing computer-executable instructions for causing a computer to design a circuit for compacting test responses, the circuit comprising:
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two or more sequential elements having respective inputs and outputs, the two or more sequential elements being operable to input a group of two or more uncompressed test response bits through the inputs of the two or more sequential elements and being further operable to output in parallel the group of two or more uncompressed test response bits through the outputs of the two or more sequential elements; a first spatial compactor comprising a plurality of first-compactor inputs and a first-compactor output, the first-compactor inputs being coupled to the outputs of the sequential elements; and a second spatial compactor comprising a plurality of second-compactor inputs and a second-compactor output, one of the plurality of second-compactor inputs being coupled to the first-compactor output. - View Dependent Claims (54, 55, 56, 57, 58, 59, 60)
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Specification