Accurate parasitic capacitance extraction for ultra large scale integrated circuits

• US 7,818,698 B2
• Filed: 10/01/2007
• Issued: 10/19/2010
• Est. Priority Date: 06/29/2007
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ho, Chia-Ming, Chen, Chien-Wen, Chang, Gwan Sin, Su, Ke-Ying
• Primary Examiner(s): Levin; Naum B
• Application Number:
  US11/865,304
• Publication Number:
  US 20090007035A1
• Time in Patent Office: 1,114 Days
• Field of Search: 716 4- 6, 324/765, 438/14, 257/48
• US Class Current: 716/136
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.

Claims

1. A method comprising the steps of:

forming a plurality of connector capacitance test structures, having substantially similar dimensions and different connector configurations from each other, wherein said plurality of connector capacitance test structures comprises a contact, a via, or combinations thereof;

measuring parasitic connector capacitance on said plurality of test structures;

creating an effective connector width table, wherein each element of said table corresponds to a primitive connector recognizable by an extraction tool and has a calculated parasitic capacitance matching to that of one of said plurality of test structures; and

generating a capacitance table corresponding to said effective connector width table.

2. The method of claim 1, wherein said test structures are MOS transistors, having substantially similar dimensions and different contact configurations.

3. The method of claim 1, wherein said connector configurations include connectors having cylindrical shapes and variations in size.

4. The method of claim 2, wherein said connector configurations have contact-to-contact and contact-to-gate-electrode distances that are each multiples of minimum design rule distances, respectively.

5. The method of claim 1, wherein each element of said effective connector width table corresponds to a connector configuration having a square-shaped primitive connector.

6. The method of claim 1, wherein said step of creating said effective connector width table includes:

providing a measured value of connector parasitic capacitance;

preparing a process characterization file, said process characterization file including a trial value of a connector area;

calculating connector parasitic capacitance value by making use of a field solver with said process characterization file; and

comparing the calculated connector value with the measured connector parasitic capacitance value to determine an effective contact width.

7. The method of claim 6, wherein said field solver has a 3-D accuracy.

8. The method of claim 1, wherein said step of generating a capacitance table corresponding to said effective connector width table includes:

inputting said effective connector width table into a field solver; and

inputting a process characterization file into said field solver, specifying process and technology parameters.