Density driven layout for RRAM configuration module

• US 7,818,703 B2
• Filed: 06/01/2007
• Issued: 10/19/2010
• Est. Priority Date: 12/08/2004
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Bolotov, Anatoli, Andreev, Alexander, Pavisic, Ivan
• Primary Examiner(s): Chiang; Jack
• Assistant Examiner(s): Tat; Binh C
• Application Number:
  US11/757,200
• Publication Number:
  US 20080016482A1
• Time in Patent Office: 1,236 Days
• Field of Search: 716 8- 12
• US Class Current: 716/122
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A system for layout of a module in an integrated circuit layout pattern has a cell library and a cell placement system. The cell library includes a plurality of cells. The cell placement system is adapted to select one or more cells from the cell library and to locally place each selected cell within the module layout so that each cell pin of the selected cells and each port of the module layout occupies a unique vertical routing track within the module layout.

Claims

1. A method comprising:

selecting a plurality of cells from a cell library for placement within a module layout pattern of an integrated circuit layout having vertical and horizontal routing tracks;

using a computer to place each of the selected cells in a different row than at least one other cell placed in the layout pattern and at a horizontal position within the module layout pattern if that position is available for placement and all cell pins of the selected cells would be positioned over unique vertical routing tracks in the module layout pattern relative to cell pins of all other cells in the module layout pattern and to ports of the module layout pattern; and

outputting data representing placement of the selected cells within the module layout pattern.

2. The method of claim 1 and further comprising:

calculating a total width of all cells to be placed in the module layout pattern;

dividing the total width by a cell utilization width of the module layout pattern to determine a quotient;

setting a number of rows of the module layout pattern equal to the quotient rounded up to a nearest integer value; and

wherein the step of placing comprises placing cells into the rows of the module layout pattern in ascending cell levels from cell Level I to a maximum cell Level such that all cell pins of all the cells are positioned over unique vertical routing tracks.

3. The method of claim 2 wherein the step of placing is repeated until all cells are placed without overlapping any placed cell within the module layout pattern.

4. The method of claim 2 wherein the step of placing comprises:

calculating an average horizontal position of all placed cells connected to the selected cell; and

positioning the selected cell as close as possible to the average horizontal position without overlapping any placed cell and such that any cell pins of the selected cell are oriented over unique vertical routing tracks relative to cell pins of already placed cells and relative to ports of the module layout pattern.

5. The method of claim 4 wherein the step of positioning comprises:

positioning the selected cell at the horizontal position in the module layout pattern corresponding to the average horizontal position of all cells connected to the selected cell;

adjusting the horizontal position by an offset distance if the selected cell overlaps a placed cell at the horizontal position; and

positioning the selected cell at the offset horizontal position and repeating the adjusting step until the selected cell is placed.

6. The method of claim 2 further comprising:

routing horizontal signal wires between cell pins and between ports of the module layout pattern and cell pins on a first available horizontal routing track beginning from a bottom horizontal routing track of the module layout pattern.

7. The method of claim 6 wherein the step of routing comprises:

locating a minimum horizontal coordinate (xmin(N)) and a maximum horizontal coordinate (xmax(N)) for each wire in a net (N), the minimum and maximum horizontal coordinates corresponding to left-most and right-most locations of any cell pin or port of the module layout pattern that is connected to the net; and

routing each horizontal signal wire from its minimum horizontal coordinate (xmin(N)) to its maximum horizontal coordinate (xmax(N)).

8. The method of claim 2 further comprising:

routing power wires on all unused vertical routing tracks of the module layout pattern.

9. The method of claim 1 wherein, for each of the plurality of selected cells, if the selected cell would overlap any other placed cell at the horizontal position, the method further comprising:

adjusting the horizontal position by an offset distance; and

repeating the placing step and the adjusting step until the selected cell is placed without overlapping any other placed cells in the module layout pattern.

10. The method of claim 1 wherein the step of selecting comprises first selecting cells coupled directly to a port of the module layout pattern, called level I cells, and then selecting cells coupled to Level I cells and not coupled directly to a port of the module layout pattern, called level II cells, the method further comprising:

repeating the steps of selecting, calculating and placing until all cells of a selected cell level are placed;

selecting a next cell level; and

repeating the steps of selecting, calculating and placing until all cells of the next cell level are placed within the module layout pattern.

11. The method of claim 1 wherein:

routing a signal wire on a first available horizontal routing track of the module layout pattern beginning from a bottom horizontal routing track of a cell row within the module layout pattern.

12. The method of claim 11 wherein if there are insufficient numbers of horizontal routing tracks within the cell row for routing a selected signal wire, the method further comprising:

expanding the module layout pattern on a top of the module layout pattern to acquire additional resources for signal routing.

13. The method of claim 1 further comprising:

routing power wires on available vertical routing tracks within the module layout pattern, the available vertical routing tracks representing tracks that are unused by the ports or placed cell pins within the module layout pattern.

14. The method of claim 1 and further comprising:

calculating an average horizontal position of all placed cells and ports of the module layout pattern to be connected to the selected cell.