Reconfigurable memory module and method
First Claim
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1. A memory system, comprising:
- a plurality of memory devices arranged in a plurality of ranks; and
a memory interface device coupled to the memory devices in each of the ranks, the memory hub being programmable to configure the memory module in a plurality of different data formats, the memory hub being operable to simultaneously address and couple data to and/or from different numbers of ranks of the memory devices in each of the different data formats.
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Abstract
A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.
324 Citations
38 Claims
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1. A memory system, comprising:
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a plurality of memory devices arranged in a plurality of ranks; and a memory interface device coupled to the memory devices in each of the ranks, the memory hub being programmable to configure the memory module in a plurality of different data formats, the memory hub being operable to simultaneously address and couple data to and/or from different numbers of ranks of the memory devices in each of the different data formats. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A memory system, comprising:
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a plurality of memory devices arranged in a plurality of ranks; and a memory hub coupled to the memory devices in each of the ranks, the memory hub being programmable to configure the memory module in a plurality of different modes, the memory hub being operable to simultaneously couple data to and/or from different each-numbers of ranks of the memory devices in each of the different data modes. - View Dependent Claims (8, 9, 10, 11)
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12. A processor-based electronic system, comprising:
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a processor operable to execute a plurality of different application programs; a controller coupled to the processor, the controller being operable to receive a memory request from the processor and to transmit a corresponding memory request from the controller; an input device coupled to the processor; an output device coupled to the processor; and a plurality of memory modules coupled to the processor, each of the memory modules comprising; a plurality of memory devices arranged in a plurality of ranks; and a memory hub coupled to the memory devices in each of the ranks and being operable to receive memory requests, the memory hub being programmable to configure the memory module in a plurality of data formats depending upon the application program being executed by the processor, each of the data formats corresponding to a respective number of ranks of memory devices that are simultaneously accessed. - View Dependent Claims (13, 14, 15)
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16. A processor-based electronic system, comprising:
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a processor operable to execute a plurality of different application programs; a controller coupled to the processor, the controller being operable to receive a memory request from the processor and to transmit a corresponding memory request from the controller; an input device coupled to the processor; an output device coupled to the processor; and a plurality of memory modules coupled to the processor, each of the memory modules comprising; a plurality of memory devices arranged in a plurality of ranks; and a memory hub coupled to the memory devices in each of the ranks and being operable to receive memory requests, the memory hub being programmable to configure the memory module in a plurality of modes depending upon the application program being executed by the processor, each of the modes corresponding to a respective number of ranks of memory devices that are simultaneously accessed. - View Dependent Claims (17, 18, 19)
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20. A processor-based electronic system, comprising:
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a processor; a controller coupled to the processor, the controller being operable to receive a memory request from the processor and to transmit a corresponding memory request from the controller; an input device coupled to the processor; an output device coupled to the processor; a memory access device other than the processor; and a plurality of memory modules coupled to the processor and to the at least one memory access device other than the processor, each of the memory modules comprising; a plurality of memory devices arranged in a plurality of ranks; and a memory hub coupled to the memory devices in each of the ranks and being operable to receive memory requests, the memory hub being programmable to configure the memory module in a plurality of different data formats depending upon whether the memory module is being accessed by the processor or the memory access device other than the processor, each of the different data formats corresponding to a respective number of ranks of memory devices that are simultaneously accessed. - View Dependent Claims (21, 22, 23, 24)
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25. A processor-based electronic system, comprising:
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a processor; a controller coupled to the processor, the controller being operable to receive a memory request from the processor and to transmit a corresponding memory request from the controller; an input device coupled to the processor; an output device coupled to the processor; a memory access device other than the processor; and a plurality of memory modules coupled to the processor and to the at least one memory access device other than the processor, each of the memory modules comprising; a plurality of memory devices arranged in a plurality of ranks; and a memory hub coupled to the memory devices in each of the ranks and being operable to receive memory requests, the memory hub being programmable to configure the memory module in a plurality of modes depending upon whether the memory module is being accessed by the processor or the memory access device other than the processor, each of the modes corresponding to a respective number of ranks of memory devices that are simultaneously accessed. - View Dependent Claims (26, 27, 28, 29)
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30. A method of accessing data in a plurality of memory devices, the method comprising:
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dividing the memory devices into a plurality of ranks; and selectively accessing the memory devices in one of a plurality of different modes, each of the different modes causing different numbers of ranks of memory devices to be simultaneously accessed. - View Dependent Claims (31, 32, 33)
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34. A method of accessing data in a plurality of memory devices, the method comprising:
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dividing the memory devices into a plurality of groups of memory devices; dividing the memory devices in each group into a plurality of ranks; accessing one of the groups of the memory devices by simultaneously accessing a first number of ranks of memory devices in the group; and accessing another of the groups of the memory devices by simultaneously accessing a second number of ranks of memory devices in the group, the second number being different from the first number. - View Dependent Claims (35, 36, 37, 38)
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Specification