Programmable task scheduler

• US 7,818,748 B2
• Filed: 12/12/2005
• Issued: 10/19/2010
• Est. Priority Date: 03/01/2000
• Status: Active Grant

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: Liu, Ming-Kang
• Primary Examiner(s): An; Meng-Ai
• Assistant Examiner(s): TRUONG, CAMQUY
• Application Number:
  US11/299,953
• Publication Number:
  US 20060090002A1
• Time in Patent Office: 1,772 Days
• Field of Search: 709/230, 707/10, 711/100, 375/219, 718/104, 718/102, 710/33
• US Class Current: 718/102
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: H04L 1/0043 Realisations of complexity reduction techniques, e.g. use of look-up tables
• CPC Class Codes: H04L 1/0052 Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
• CPC Class Codes: H04L 12/2856 Access arrangements, e.g. Internet access asynchronous transfer mode networks H04L12/5601; broadband local area networks H04L12/2801; optical access or distribution networks H04Q11/0067; access to open networks H04L12/5691; digital subscriber line end-user equipment and bit-level processing of data on a PSTN-based network H04M11/00; home network gateways H04L12/2834; wireless access networks H04W
• CPC Class Codes: H04L 12/289 Single service
• CPC Class Codes: H04L 2012/5665 Interaction of ATM with other protocols
• CPC Class Codes: H04L 2012/6478 Digital subscriber line, e.g. DSL, ADSL, HDSL, XDSL, VDSL
• CPC Class Codes: H04L 27/2601 Multicarrier modulation systems
• CPC Class Codes: H04L 27/2626 Arrangements specific to the transmitter only
• CPC Class Codes: H04L 27/2647 Arrangements specific to the receiver only equalisation H04L27/01
• CPC Class Codes: H04M 11/062 using different frequency bands for speech and other data
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A task scheduler for a TC subsystem is disclosed. The task scheduler is responsible for responding to computation block requests from the TC subsystem, and retrieving/storing data objects for such computation blocks. The task scheduler thus facilitates a type of logical pipeline by exchanging such data objects with a common TC memory used by each computation block. The task scheduler generally includes a queue, a state machine and a bus master for satisfying the data object requests.

Claims

1. An apparatus comprising:

a task scheduler to retrieve and/or store data objects;

a function block to provide a request to the task scheduler, the request associated with a data object from among the data objects retrievable and/or storable by the task scheduler;

a first memory to store the request, the request having an identifier field to store an identifier associated with the function block, and the request having a field to store a computation count associated with the function block, the computation count correlated to a number of computations of use of the function block;

second memory to store a first table; and

a functional unit to read an entry stored in the first table based upon the identifier and the computation count, the computation count used to locate the entry in the first table;

wherein the entry indicates a memory address for the data object;

wherein the second memory further stores a second table; and

the functional unit, in response to reading the identifier, reads an offset address stored in the second table, wherein the functional unit reads the entry stored in the first table based upon the offset address and the computation count.

2. The apparatus as set forth in claim 1, wherein the second memory comprises at least two memory devices.

3. The apparatus as set forth in claim 1, wherein the second memory is logically partitioned into at least a first memory block and a second memory block, wherein the first table is stored in the first memory block and the second table is stored in the second memory block.

4. The apparatus as set forth in claim 1, wherein the request is a download request so that the functional unit causes a memory read of the data object according to the memory address.

5. The apparatus as set forth in claim 1, wherein the request is an upload request so that the functional unit causes a memory write of the data object according to the memory address.

6. The apparatus as set forth in claim 1, the function block comprising a register to store the identifier.

7. The apparatus as set forth in claim 1, the function block comprising a register to store a computation round number.

8. The apparatus as set forth in claim 7, wherein the computation round number is updated when the function block completes an operation on the data object.

9. The apparatus as set forth in claim 8, wherein the computation round number is re-set to a pre-determined value for a new discrete multi-tone (DMT) symbol time.

10. The apparatus as set forth in claim 1, wherein the computation count is updated when the function block completes an operation on the data object.

11. The apparatus as set forth in claim 1, wherein the computation count is re-set to a pre-determined value for a new discrete multi-tone (DMT) symbol time.

12. The apparatus as set forth in claim 1, wherein the data object is indicative of a discrete multi-tone (DMT) symbol.

13. The apparatus as set forth in claim 12, wherein the computation round number is updated when the function block completes an operation on the data object.

14. The apparatus as set forth in claim 13, wherein the computation round number is re-set to a pre-determined value for a new discrete multi-tone (DMT) symbol time.

15. The apparatus as set forth in claim 12, wherein the computation round number is re-set to a pre-determined value for a new discrete multi-tone (DMT) symbol time.

16. The apparatus as set forth in claim 1, the first memory comprising a queue.

17. The apparatus as set forth in claim 1, comprising a memory device, the memory device comprising the first memory and the second memory.

18. An apparatus comprising:

an arrangement of components to process at least one channel symbol, corresponding to a communication channel, during a first channel symbol time, the arrangement including;

a memory in which to store data objects associated with channel symbols;

a task scheduler to retrieve and/or store the data objects;

a function block to provide a request to the task scheduler for a data object, the requested data object being associated with a channel symbol, the request comprising an identifier to identify the function block and the request comprising a computation count, the computation count correlated to a number of computations of use of the function block, wherein the computation count is updated in response to the function block performing an operation on the data object; and

a functional unit to use the identifier and the computation count to provide a memory address for the data object, the computation count used to locate an entry in a table to provide the memory address;

wherein the computation count is re-set to a pre-assigned number for a second channel symbol time subsequent to the first channel symbol time.