Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication

• US 7,820,513 B2
• Filed: 10/28/2008
• Issued: 10/26/2010
• Est. Priority Date: 06/27/2003
• Status: Expired due to Term

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Chau, Robert S., Doyle, Brian S., Rios, Rafael, Hareland, Scott A., Datta, Suman, Linton, Tom
• Primary Examiner(s): Such; Matthew W
• Application Number:
  US12/259,464
• Publication Number:
  US 20090061572A1
• Time in Patent Office: 728 Days
• Field of Search: 257347-354, 257/E21.404, 257/E21.415, 257/E21.438, 257/E1.444, 438/157, 438/280, 438283-284, 438/300
• US Class Current: 438/283
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Claims

1. A method of forming a nonplanar transistor comprising:

forming a semiconductor body having a top surface and bottom surface and a pair of laterally opposite sidewalls on an insulating substrate;

forming a sacrificial gate electrode above said top surface of said semiconductor body and adjacent to said laterally opposite sidewalls of said semiconductor body, said sacrificial gate electrode having a pair of laterally opposite sidewalls;

placing dopants into said semiconductor body on opposite sides of said sacrificial gate electrode to form a pair of source/drain extensions on opposite sides of said gate electrode;

forming a pair of sidewall spacers along laterally opposite sidewalls of said sacrificial gate electrode;

forming silicon on said semiconductor body adjacent to said sidewall spacers;

placing dopants into said silicon and into said semiconductor body in alignment with said sidewall spacers;

forming a silicide on said silicon formed on said semiconductor body adjacent to said sidewall spacers;

forming a dielectric layer over said silicide, said sacrificial gate electrode and said sidewall spacers;

planarizing said dielectric layer until the top surface of said dielectric layer is planar with the top surface of said sacrificial gate electrode and said sacrificial gate electrode is exposed;

removing said sacrificial gate electrode to expose the channel region of said semiconductor body and said insulating substrate;

removing a portion of said insulating substrate in said opening beneath said semiconductor body to expose at least a portion of said bottom surface of said semiconductor body;

forming a gate dielectric layer on said top surface and said sidewalls of said semiconductor body in said opening and on said portion of said exposed bottom surface of said semiconductor body;

blanket depositing a gate electrode material on said gate dielectric layer and into said opening and on said gate dielectric layer on said top surface of said semiconductor body, adjacent to said gate dielectric on said sidewalls of said semiconductor body, and beneath said gate dielectric on said exposed portion of said bottom surface of said semiconductor body; and

removing said gate electrode material from the top surface of said dielectric film to form a gate electrode.

2. The method of claim 1 wherein semiconductor body is formed from single crystalline silicon.

3. The method of claim 2 wherein said insulating substrate comprises a lower monocrystalline silicon substrate and a top silicon insulating film.