Thin film transistor

• US 7,821,012 B2
• Filed: 03/04/2009
• Issued: 10/26/2010
• Est. Priority Date: 03/18/2008
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Jinbo, Yasuhiro
• Primary Examiner(s): Pham; Long
• Application Number:
  US12/397,460
• Publication Number:
  US 20090236601A1
• Time in Patent Office: 601 Days
• Field of Search: 257/72, 257/288, 257/E29.273, 257/E33.053
• US Class Current: 257/72
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate

Abstract

A thin film transistor includes a first insulating layer covering the gate electrode layer; source and drain regions which at least partly overlaps with the gate electrode layer; a pair of second insulating layers which is provided apart from each other in a channel length direction over the first insulating layer and which at least partly overlaps with the gate electrode layer and the pair of impurity semiconductor layers; a pair of microcrystalline semiconductor layers provided apart from each other on and in contact with the second insulating layers; and an amorphous semiconductor layer covering the first insulating layer, the pair of second insulating layers, and the pair of microcrystalline semiconductor layers and which extends to exist between the pair of microcrystalline semiconductor layers. The first insulating layer is a silicon nitride layer and each of the pair of the second insulating layers is a silicon oxynitride layer.

Claims

1. A thin film transistor comprising:

a gate electrode layer;

a first insulating layer over the gate electrode layer;

a pair of second insulating layers over the first insulating layer, wherein the pair of second insulating layers is provided apart from each other in a channel length direction and overlaps with at least a part of the gate electrode layer;

a pair of microcrystalline semiconductor layers over the pair of second insulating layers, wherein the pair of microcrystalline semiconductor layers is provided apart from each other and in contact with the pair of second insulating layers;

an amorphous semiconductor layer over the first insulating layer, the pair of second insulating layers, and the pair of microcrystalline semiconductor layers, wherein a part of the amorphous semiconductor layer is provided between the pair of microcrystalline semiconductor layers; and

a pair of impurity semiconductor layers over the amorphous semiconductor layer, wherein the pair of impurity semiconductor layers overlaps with at least a part of the gate electrode layer and is provided apart from each other so as to form a source region and a drain region,

wherein the first insulating layer is a silicon nitride layer, and each of the pair of second insulating layers is a silicon oxynitride layer.

4. The thin film transistor according to claim 1,

wherein a first portion of the first insulating layer which overlaps with the second insulating layers is thicker than a second portion of the first insulating layer which does not overlap with the second insulating layers and overlaps with the gate electrode layer.

7. The thin film transistor according to claim 1,

wherein a side surface of the microcrystalline semiconductor layer is aligned with a side surface of the second insulating layer.

10. The thin film transistor according to claim 1,

wherein the pair of microcrystalline semiconductor layers has an electrical conductivity of greater than or equal to 1×

10<sup>−

5</sup> S·

cm<sup>−

1</sup> and less than or equal to 5×

10<sup>−

2</sup> S·

cm<sup>−

1</sup>.

13. The thin film transistor according to claim 1,

wherein the pair of the microcrystalline semiconductor layers includes an impurity element serving as a donor.

16. The thin film transistor according to claim 13,

wherein a concentration of the impurity element of the pair of microcrystalline semiconductor layers is greater than or equal to 1×

10¹⁸ cm<sup>−

3</sup> and less than or equal to 1×

10²¹ Cm<sup>−

3</sup>.

19. The thin film transistor according to claim 1,

wherein the amorphous semiconductor layer is an amorphous silicon layer.

22. The thin film transistor according to claim 1,

wherein the pair of microcrystalline semiconductor layers comprises phosphorus and silicon.

2. A thin film transistor comprising:

a gate electrode layer;

a first insulating layer over the gate electrode layer;

an amorphous semiconductor layer over the first insulating layer and in contact with at least a part of the first insulating layer;

a pair of impurity semiconductor layers over the amorphous semiconductor layer, wherein the pair of impurity semiconductor layers is provided apart from each other so as to form a source region and a drain region;

a pair of second insulating layers between the first insulating layer and the amorphous semiconductor layer, wherein the pair of second insulating layers is provided apart from each other; and

a pair of microcrystalline semiconductor layers on and in contact with the pair of the second insulating layers, wherein the pair of microcrystalline semiconductor layers is provided apart from each other and overlaps with at least a part of the pair of impurity semiconductor layers,

wherein the first insulating layer is a silicon nitride layer and each of the pair of the second insulating layers is a silicon oxynitride layer.

5. The thin film transistor according to claim 2,

wherein a first portion of the first insulating layer which overlaps with the second insulating layers is thicker than a second portion of the first insulating layer which does not overlap with the second insulating layers and overlaps with the gate electrode layer.

8. The thin film transistor according to claim 2,

wherein a side surface of the microcrystalline semiconductor layer is aligned with a side surface of the second insulating layer.

11. The thin film transistor according to claim 2,

wherein the pair of microcrystalline semiconductor layers has an electrical conductivity of greater than or equal to 1×

10<sup>−

5</sup> S·

cm<sup>−

1</sup> and less than or equal to 5×

10<sup>−

2</sup> S·

cm<sup>−

1</sup>.

14. The thin film transistor according to claim 2,

wherein the pair of the microcrystalline semiconductor layers includes an impurity element serving as a donor.

17. The thin film transistor according to claim 14,

wherein a concentration of the impurity element of the pair of microcrystalline semiconductor layers is greater than or equal to 1×

10¹⁸ cm<sup>−

3</sup> and less than or equal to 1×

10²¹ cm<sup>−

1</sup>.

20. The thin film transistor according to claim 2,

wherein the amorphous semiconductor layer is an amorphous silicon layer.

23. The thin film transistor according to claim 2,

wherein the pair of microcrystalline semiconductor layers comprises phosphorus and silicon.

3. A thin film transistor comprising:

a gate electrode layer;

a first insulating layer over the gate electrode layer;

a pair of second insulating layers over the first insulating layer,

a pair of microcrystalline semiconductor layers on and in contact with the pair of second insulating layers;

an amorphous semiconductor layer over the pair of microcrystalline semiconductor layers; and

a source region and a drain region over the amorphous semiconductor layer,

wherein a portion of the amorphous semiconductor layer is between the pair of microcrystalline semiconductor layers, and

wherein the first insulating layer is a silicon nitride layer and each of the pair of second insulating layers is a silicon oxynitride layer.

6. The thin film transistor according to claim 3,

wherein a first portion of the first insulating layer which overlaps with the second insulating layers is thicker than a second portion of the first insulating layer which does not overlap with the second insulating layers and overlaps with the gate electrode layer.

9. The thin film transistor according to claim 3,

wherein a side surface of the microcrystalline semiconductor layer is aligned with a side surface of the second insulating layer.

12. The thin film transistor according to claim 3,

wherein the pair of microcrystalline semiconductor layers has an electrical conductivity of greater than or equal to 1×

10<sup>−

5</sup> S·

cm<sup>−

1</sup> and less than or equal to 5×

10<sup>−

2</sup> S·

cm<sup>−

1</sup>.

15. The thin film transistor according to claim 3,

wherein the pair of the microcrystalline semiconductor layers includes an impurity element serving as a donor.

18. The thin film transistor according to claim 15,

wherein a concentration of the impurity element of the pair of microcrystalline semiconductor layers is greater than or equal to 1×

10¹⁸ cm<sup>−

3</sup> and less than or equal to 1×

10²¹ cm<sup>−

3</sup>.

21. The thin film transistor according to claim 3,

wherein the amorphous semiconductor layer is an amorphous silicon layer.

24. The thin film transistor according to claim 3,

wherein the pair of microcrystalline semiconductor layers comprises phosphorus and silicon.