Nonvolatile semiconductor memory and method for manufacturing the same

• US 7,821,058 B2
• Filed: 01/08/2008
• Issued: 10/26/2010
• Est. Priority Date: 01/10/2007
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ozawa, Yoshio, Sato, Mitsuru, Fukuzumi, Yoshiaki, Katsumata, Ryota, Kito, Masaru, Aochi, Hideaki, Kidoh, Masaru, Tanaka, Hiroyasu, Matsuoka, Yasuyuki
• Primary Examiner(s): Warren; Matthew E
• Assistant Examiner(s): SPALLA, DAVID C
• Application Number:
  US11/970,992
• Publication Number:
  US 20080173932A1
• Time in Patent Office: 1,022 Days
• Field of Search: 257/275, 257/329, 257/E21.646, 257/E21.654, 257/E21.657, 257/E21.659, 257/E27.084, 257/E21.652, 257/E27.096, 438/212, 438/239, 438/242
• US Class Current: 257/324
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory including: a columnar semiconductor; a charge storage insulating film including: a first insulating film formed around the columnar semiconductor, a charge storage film formed around the first insulating film, and a second insulating film formed around the charge storage film; an electrode extending two-dimensionally to surround the charge storage insulating film, the electrode having a groove; and a metal silicide formed on a sidewall of the groove.

Claims

1. A nonvolatile semiconductor memory comprising:

a semiconductor substrate;

a plurality of columnar semiconductors formed on the semiconductor substrate to vertically extend in parallel with one another and to be in a matrix as viewed from above;

plurality of charge storage insulating films formed around the columnar semiconductors, respectively;

at least two of plate-like electrodes each extending two-dimensionally to be perpendicular to the columnar semiconductors and to surround the charge storage insulating films, each electrode respectively forming a memory transistor with the columnar semiconductors and the charge storage insulating films, at least one groove vertically passing through the electrodes to expose sidewalls of the electrodes; and

a plurality of metal silicides formed on the exposed sidewalls of the electrodes, respectively.

2. The nonvolatile semiconductor memory according to claim 1, wherein the columnar semiconductor, the charge storage insulating film and the electrode form a memory transistor operated in a depression mode.

3. The nonvolatile semiconductor memory according to claim 1, wherein the columnar semiconductor comprises a plurality of columnar semiconductors;

wherein the charge storage insulating film comprises a plurality of charge storage insulating films respectively formed around the plurality of columnar semiconductors;

wherein the electrode is formed to surround the plurality of charge storage insulating films;

wherein the groove comprises a plurality of grooves; and

wherein the metal silicide is formed on respective sidewalls of the plurality of grooves.

4. The nonvolatile semiconductor memory according to claim 3, wherein the electrode comprises a plurality of linear portions separated from each other by the plurality of grooves.

5. The nonvolatile semiconductor memory according to claim 4, wherein the plurality of linear portions are connected with each other on one end of the electrode.

6. The nonvolatile semiconductor memory according to claim 4, wherein the plurality of linear portions are connected with each other on both ends of the electrode.

7. The nonvolatile semiconductor memory according to claim 3, wherein the plurality of columnar semiconductors are formed in parallel;

and

wherein the plurality of columnar semiconductors are disposed in a matrix.

8. The nonvolatile semiconductor memory according to claim 1, wherein the electrode comprises a plurality of electrodes alternately laminated with a plurality of insulators;

and

wherein each of the plurality of electrodes surrounds the charge storage insulating film.

9. The nonvolatile semiconductor memory according to claim 8, wherein the columnar semiconductor, the plurality of electrodes and the charge storage insulating film form a memory string having a plurality of memory transistors operated in a depression mode.

10. The nonvolatile semiconductor memory according to claim 1 further comprising:

a gate insulating film formed around the columnar semiconductor above the charge storage insulating film;

a second electrode surrounds the gate insulating film; and

a second metal silicide formed on a sidewall of the second electrode.

11. The nonvolatile semiconductor memory according to claim 10, wherein the columnar semiconductor, the gate insulating film and the second electrode form a selection transistor operated in a depression mode.

12. The nonvolatile semiconductor memory according to claim 1, wherein the metal silicide comprises at least one of a titanium silicide, a cobalt silicide and a nickel silicide.

13. The nonvolatile semiconductor memory according to claim 1 further comprising:

a plurality of gate insulating films formed around the columnar semiconductors above the charge storage insulating films, respectively;

a gate electrode extending two-dimensionally to be perpendicular to the columnar semiconductors and to surround the gate insulating films, the gate electrode respectively forming a select transistor with the columnar semiconductors and the gate insulating films, at least one groove vertically passing through the gate electrode to expose a sidewall of the gate electrode; and

a second metal silicide formed on the exposed sidewall of the gate electrode.

14. The nonvolatile semiconductor memory according to claim 13, wherein the second metal silicide comprises at least one of a titanium silicide, a cobalt silicide and a nickel silicide.

15. The nonvolatile semiconductor memory according to claim 13, wherein a plurality of grooves are formed in each electrode;

and

wherein a first metal silicide is formed on sidewalls of the plurality of grooves.