Patterned backside stress engineering for transistor performance optimization

• US 7,821,073 B2
• Filed: 04/03/2008
• Issued: 10/26/2010
• Est. Priority Date: 09/24/2004
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Baskaran, Rajashree, Vandentop, Gilroy J.
• Primary Examiner(s): Dickey; Thomas L
• Assistant Examiner(s): Erdem; Fazli
• Application Number:
  US12/061,935
• Publication Number:
  US 20080237729A1
• Time in Patent Office: 936 Days
• Field of Search: 257/369, 257/707, 257/E27.062, 257/375, 257/E21.476, 257/E21.249
• US Class Current: 257/369
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054

Abstract

Some embodiments of the present invention include selectively inducing back side stress opposite transistor regions to optimize transistor performance.

Claims

1. An apparatus comprising:

a first surface of a substrate haying a first transistor type region and a second transistor type region; and

a heat spreader attached to a substrate surface opposite the first surface, the heat spreader having a portion opposite the first transistor type region that is thinner than a portion opposite the second transistor type region, wherein the portion opposite the first transistor type region is about 0.1 to 1.25 mm thick and the portion opposite the second transistor type region is about 1.25 to 2.75 mm thick.

2. An apparatus comprising:

a first surface of a substrate having a first transistor type region and a second transistor type region; and

a heat spreader attached to a substrate surface opposite the first surface, the heat spreader having a portion opposite the first transistor type region that is thinner than a portion opposite the second transistor type region, wherein the portion opposite the first transistor type region is about 0.25 to 1.1 mm thick and the portion opposite the second transistor type region is about 1.25 to 2.75mm thick.

3. An apparatus comprising:

a first surface of a substrate haying a first transistor type region and a second transistor type region; and

a heat spreader attached to a substrate surface opposite the first surface, the heat spreader haying a portion opposite the first transistor type re gion that is thinner than a portion opposite the second transistor type region, wherein the portion opposite the first transistor type region is about 0.5 to 1.0 mm thick and the portion opposite the second transistor type region is about 1.5 to 2.5 mm thick.

4. The apparatus of claim 3, further comprising:

a thermal interface material between the substrate surface opposite the first surface and the heat spreader.

5. The apparatus of claim 4, wherein the heat spreader includes copper and the thermal interface material includes gold-tin.