Low power output driver
First Claim
1. A low power output driver comprising:
- (a) one of a series-regulated and a switching-mode-regulated reduced voltage source that receives a supply voltage and outputs a continuously regulated reduced voltage that is a lower voltage than the supply voltage;
(b) a first driver input that receives a first logic signal;
(c) a second driver input that receives a second logic signal;
(d) a first driver output that outputs a first output signal;
(e) a second driver output that outputs a second output signal;
(f) a first n-type metal oxide semiconductor (NMOS) having a gate, a source and a drain, the source and the drain of the first NMOS being electrically coupled between the reduced voltage VL and the first driver output, the gate of the first NMOS being electrically coupled to the first driver input;
(g) a second NMOS having a gate, a source and a drain, the source and the drain of the second NMOS being electrically coupled between the first driver output and a constant voltage internal ground, the gate of the second NMOS being electrically coupled to the second driver input;
(h) a third NMOS having a gate, a source and a drain, the source and the drain of the third NMOS being electrically coupled between the reduced voltage VL and the second driver output, the gate of the third NMOS being electrically coupled to the second driver input; and
(i) a fourth NMOS having a gate, a source and a drain, the source and the drain of the fourth NMOS being electrically coupled between the second driver output and the constant voltage internal ground, the gate of the fourth NMOS being electrically coupled to the first driver input,when the first driver input is high and the second driver input is low, the first NMOS and the fourth NMOS are gated on, the first driver output is raised to the reduced voltage VL, the second driver output is pulled down to the constant voltage internal ground, and current through the first NMOS and the fourth NMOS is reduced to zero,when the second driver input is high and the first driver input is low, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage VL, the first driver output is pulled down to the constant voltage internal ground, and current through the second NMOS and the third NMOS is reduced to zero, andthe constant voltage internal ground differentiates the driver output raised to the reduced voltage from the driver output pulled down to the constant voltage internal ground.
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Accused Products
Abstract
A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that are cross-connected between the reduced voltage and the first and second driver outputs or a constant voltage internal ground. When the second input is high, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the constant voltage ground.
82 Citations
22 Claims
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1. A low power output driver comprising:
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(a) one of a series-regulated and a switching-mode-regulated reduced voltage source that receives a supply voltage and outputs a continuously regulated reduced voltage that is a lower voltage than the supply voltage; (b) a first driver input that receives a first logic signal; (c) a second driver input that receives a second logic signal; (d) a first driver output that outputs a first output signal; (e) a second driver output that outputs a second output signal; (f) a first n-type metal oxide semiconductor (NMOS) having a gate, a source and a drain, the source and the drain of the first NMOS being electrically coupled between the reduced voltage VL and the first driver output, the gate of the first NMOS being electrically coupled to the first driver input; (g) a second NMOS having a gate, a source and a drain, the source and the drain of the second NMOS being electrically coupled between the first driver output and a constant voltage internal ground, the gate of the second NMOS being electrically coupled to the second driver input; (h) a third NMOS having a gate, a source and a drain, the source and the drain of the third NMOS being electrically coupled between the reduced voltage VL and the second driver output, the gate of the third NMOS being electrically coupled to the second driver input; and (i) a fourth NMOS having a gate, a source and a drain, the source and the drain of the fourth NMOS being electrically coupled between the second driver output and the constant voltage internal ground, the gate of the fourth NMOS being electrically coupled to the first driver input, when the first driver input is high and the second driver input is low, the first NMOS and the fourth NMOS are gated on, the first driver output is raised to the reduced voltage VL, the second driver output is pulled down to the constant voltage internal ground, and current through the first NMOS and the fourth NMOS is reduced to zero, when the second driver input is high and the first driver input is low, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage VL, the first driver output is pulled down to the constant voltage internal ground, and current through the second NMOS and the third NMOS is reduced to zero, and the constant voltage internal ground differentiates the driver output raised to the reduced voltage from the driver output pulled down to the constant voltage internal ground. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A low power output driver comprising:
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(a) one of a series-regulated and a switching-mode-regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage; (b) a first driver input that receives a first logic signal; (c) a second driver input that receives a second logic signal; (d) a first driver output that outputs a first output signal; (e) a second driver output that outputs a second output signal; (f) a single-ended load connected to both the first driver output and the second driver output; (g) a first n-type metal oxide semiconductor (NMOS) having a gate, a source and a drain, the source and the drain of the first NMOS being electrically coupled between the reduced voltage VL and the first driver output, the gate of the first NMOS being electrically coupled to the first driver input; (h) a second NMOS having a gate, a source and a drain, the source and the drain of the second NMOS being electrically coupled between the first driver output and a constant voltage internal ground, the gate of the second NMOS being electrically coupled to the second driver input; (i) a third NMOS having a gate, a source and a drain, the source and the drain of the third NMOS being electrically coupled between the reduced voltage VL and the second driver output, the gate of the third NMOS being electrically coupled to the second driver input; and (j) a fourth NMOS having a gate, a source and a drain, the source and the drain of the fourth NMOS being electrically coupled between the second driver output and the constant voltage internal ground, the gate of the fourth NMOS being electrically coupled to the first driver input, when the first driver input is high and the second driver input is low, the first NMOS and the fourth NMOS are gated on, the first driver output is raised to the reduced voltage and the second driver output is pulled down to the constant voltage internal ground, when the second driver input is high and the first driver input is low, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the constant voltage internal ground. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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21. A low power output driver comprising:
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(a) one of a series-regulated and a switching-mode-regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage, the reduced voltage source includes a voltage source input that receives the supply voltage and a voltage source output that outputs the regulated reduced voltage VL, the reduced voltage source including; (i) a voltage source MOS having a gate, a source and a drain, the source and the drain of the voltage source MOS being electrically coupled between the voltage source input and voltage source output, and (ii) an operational amplifier having a non-inverting input, an inverting input and an amplifier output, the non-inverting input being electrically coupled to an internal reference, the inverting input being electrically coupled to the voltage source output and the amplifier output being electrically coupled to the gate of the voltage source MOS; (b) a first driver input that receives a first logic signal; (c) a second driver input that receives a second logic signal; (d) a first driver output that outputs a first output signal; (e) a second driver output that outputs a second output signal; (f) a first n-type metal oxide semiconductor (NMOS) having a gate, a source and a drain, the source and the drain of the first NMOS being electrically coupled between the reduced voltage VL and the first driver output, the gate of the first NMOS being electrically coupled to the first driver input; (g) a second NMOS having a gate, a source and a drain, the source and the drain of the second NMOS being electrically coupled between the first driver output and a constant voltage internal ground, the gate of the second NMOS being electrically coupled to the second driver input; (h) a third NMOS having a gate, a source and a drain, the source and the drain of the third NMOS being electrically coupled between the reduced voltage VL and the second driver output, the gate of the third NMOS being electrically coupled to the second driver input; and (i) a fourth NMOS having a gate, a source and a drain, the source and the drain of the fourth NMOS being electrically coupled between the second driver output and the constant voltage internal ground, the gate of the fourth NMOS being electrically coupled to the first driver input, when the first driver input is high and the second driver input is low, the first NMOS and the fourth NMOS are gated on, the first driver output is raised to the reduced voltage, the second driver output is pulled down to the constant voltage internal ground, and current through the first NMOS and the fourth NMOS is reduced to zero, when the second input is high and the first driver input is low, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage VL, the first driver output is pulled down to the constant voltage internal ground, and current through the second NMOS and the third NMOS is reduced to zero, and the constant voltage internal ground differentiates the driver output raised to the reduced voltage VL from the driver output pulled down to the constant voltage internal ground.
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22. A low power output driver comprising:
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(a) one of a series-regulated and a switching-mode-regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage, the reduced voltage source includes a voltage source input that receives the supply voltage and a voltage source output that outputs the regulated reduced voltage VL, the reduced voltage source including; (i) a voltage source bipolar transistor, the voltage source bipolar transistor being electrically coupled between the voltage source input and voltage source output, and (ii) an operational amplifier having a non-inverting input, an inverting input and an amplifier output, the non-inverting input being electrically coupled to an internal reference, the inverting input being electrically coupled to the voltage source output and the amplifier output being electrically coupled to a gate of the voltage source bipolar transistor; (b) a first driver input that receives a first logic signal; (c) a second driver input that receives a second logic signal; (d) a first driver output that outputs a first output signal; (e) a second driver output that outputs a second output signal; (f) a first n-type metal oxide semiconductor (NMOS) having a gate, a source and a drain, the source and the drain of the first NMOS being electrically coupled between the reduced voltage VL and the first driver output, the gate of the first NMOS being electrically coupled to the first driver input; (g) a second NMOS having a gate, a source and a drain, the source and the drain of the second NMOS being electrically coupled between the first driver output and a constant voltage internal ground, the gate of the second NMOS being electrically coupled to the second driver input; (h) a third NMOS having a gate, a source and a drain, the source and the drain of the third NMOS being electrically coupled between the reduced voltage VL and the second driver output, the gate of the third NMOS being electrically coupled to the second driver input; and (i) a fourth NMOS having a gate, a source and a drain, the source and the drain of the fourth NMOS being electrically coupled between the second driver output and the constant voltage internal ground, the gate of the fourth NMOS being electrically coupled to the first driver input, when the first driver input is high and the second driver input is low, the first NMOS and the fourth NMOS are gated on, the first driver output is raised to the reduced voltage, the second driver output is pulled down to the constant voltage internal ground, and current through the first NMOS and the fourth NMOS is reduced to zero, when the second input is high and the first driver input is low, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage VL, the first driver output is pulled down to the constant voltage internal ground, and current through the second NMOS and the third NMOS is reduced to zero, and the constant voltage internal ground differentiates the driver output raised to the reduced voltage VL from the driver output pulled down to the constant voltage internal ground.
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Specification